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BORROWED FROM SEMICONDUCTORS, BUILT FOR PHOTONICS: THE PACKAGING MOVE AI CONNECTIVITY NEEDS
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Engineers and technologists interested in advanced packaging solutions for AI infrastructure and optical interconnects.
TL;DR
This video explains how advanced semiconductor packaging techniques, specifically fan-out wafer-level packaging, are being adapted for photonics. This allows for the integration of Vixel lasers and photodiode chips with CMOS for high-bandwidth, short-range AI connectivity, offering an alternative to silicon photonics.
Key Takeaways
- Advanced packaging techniques, borrowed from semiconductor manufacturing, are crucial for enabling the high-density connectivity required by AI scale-up applications.
- Vixel technology, already used in billions of devices for 3D sensing, offers a viable, high-bandwidth alternative to silicon photonics for short-range optical links.
- Fan-out wafer-level packaging (FOWLP) is a demonstrated, high-volume technology suitable for integrating multiple heterogeneous dies like Vixels, photodiodes, TIAs, and drivers into compact optical engines.
- The presented optical engine integrates 35 Vixel devices with CMOS die using FOWLP, demonstrating a path towards scalable AI connectivity solutions.
- Leveraging existing OSAT (Outsourced Semiconductor Assembly and Test) design rules for FOWLP simplifies manufacturing and reduces risk, allowing focus on critical areas like testing and fiber integration.
- The FOWLP process involves wafer reconstitution, overmolding, back grinding to reveal copper pillars, and building up redistribution layers (RDL) for interconnectivity.
- While the prototype used commercially available TIAs and drivers, a custom ASIC could further optimize the design for higher channel density and performance.
- The FOWLP approach can be adapted for even denser integration, potentially enabling true co-packaged optics by stacking dies or using interposers.
In This Video
- 00:00Introduction to Advanced Packaging
The speaker introduces themselves as a packaging expert with extensive experience at Intel and Lumentum, highlighting their background in advanced packaging.
- 01:10AI Scale-Up and Photonics Demands
The presentation focuses on applying advanced packaging to integrate 35 devices with CMOS die for compact optic engines, addressing AI scale-up demands.
- 02:11Vixel Technology as an Alternative
Vixel technology is presented as an alternative to silicon photonics for AI scale-up, offering high bandwidth and a mature manufacturing ecosystem.
- 03:49Packaging Challenges and Solutions
The speaker discusses the challenge of packaging Vixels and introduces fan-out wafer-level packaging (FOWLP) as a manufacturable solution.
- 05:03FOWLP Package Structure
The FOWLP package integrates Vixels, photodiodes, TIA, and drivers, using RDL layers and a BGA for interconnect, suitable for PCB or die stack integration.
- 06:45Manufacturing Compliance and Process
The packaging process was 100% compliant with OSAT design rules, involving wafer reconstitution, overmolding, back grinding, and RDL fabrication.
- 08:59RDL and Design Rules
Two layers of RDL were implemented using medium density design rules, offering a balance between density and manufacturability compared to PCB or front-end fab.
Questions & Answers
What is the main challenge AI scale-up presents for connectivity?
AI scale-up demands high bandwidth and low latency connectivity, requiring solutions like co-packaged optics to meet the increasing data transfer needs.
What is Vixel technology and its benefits for AI connectivity?
Vixel technology, used in iPhones for face recognition, offers an established high-volume manufacturing ecosystem and is suitable for short-range, high-bandwidth links within racks.
How does Vixel technology compare to silicon photonics for AI?
Vixels provide an alternative to silicon photonics, offering diversity in solutions for customers and addressing the limitations of relying on a single technology.
What packaging technique was used for the compact optic engine?
A fan-out wafer-level package (FOWLP) was used, a standard, high-volume technology that allows for heterogeneous integration of multiple dies.
What are the components within the fan-out wafer-level package?
The package includes Vixels, photodiodes, a TIA, and a driver, all encased in mold material with two layers of RDL and a BGA for interconnect.
Was the packaging process compatible with existing manufacturing flows?
Yes, the fan-out wafer-level package process flow was 100% within the OSAT's design rules, requiring no new inventions and simplifying the assembly.
Key Terms
- Co-packaged optics — Integrating optical components directly with electronic components on the same package for higher bandwidth and lower power consumption.
- Vixel technology — A type of laser technology used for 3D sensing, offering high bandwidth and suitable for short-range optical links.
- Fan-out wafer-level package (FOWLP) — An advanced packaging technique that allows for redistribution of signals from a die to a larger area, enabling heterogeneous integration.
- Heterogeneous integration — Combining different types of semiconductor devices or components onto a single package or substrate.