Full Transcript
https://www.youtube.com/watch?v=spPFSk1ycO4
[00:00] Thanks Richard for the uh for the quick intro and thanks a lot for inviting me here to uh hopefully sunny Barcelona um.
[00:08] to talk about wafer scale optical interconnect um and what I'll be doing is I'll be showing how silicon photonics and advanced 3D assembly can be combined to uh push a new generation of photonics for um AI compute infrastructure.
[00:23] So I don't think that at this conference I really need to uh explain in depth what uh AI compute hardware looks like but just to set the the the background um today AI uh compute infrastructure mainly relies on uh a set of CPUs um each having accelerator GPUs associated with them.
[00:45] The accelerator GPUs have HBM sitting right next to them and then typically in the latest generations you also have IO chiplets um facing first a scaleup network.
[00:56] The scaleup network itself uh its
[01:01] scaleup network itself uh its functionality is to um have or
[01:05] functionality is to um have or effectively convert all the GPU dice
[01:07] effectively convert all the GPU dice into let's call it one single die GPU
[01:10] into let's call it one single die GPU but of a huge size far beyond what we
[01:14] but of a huge size far beyond what we can do on a single reticle.
[01:16] Um and then in addition to that you have the scale
[01:18] in addition to that you have the scale out network which is responsible for
[01:20] out network which is responsible for moving traffic between the uh compute
[01:24] moving traffic between the uh compute elements let's call them that way.
[01:26] So you would have in these uh in that
[01:28] you would have in these uh in that infrastructure these two uh networks the
[01:31] infrastructure these two uh networks the scale out which today is optical already
[01:34] scale out which today is optical already and then the scaleup network which today
[01:36] and then the scaleup network which today is in most cases constrained to a single
[01:39] is in most cases constrained to a single rack and is fully based on copper
[01:42] rack and is fully based on copper interconnect.
[01:44] interconnect. Now if you look at the scale up domain
[01:46] Now if you look at the scale up domain and then in particular at how many GPUs
[01:49] and then in particular at how many GPUs we have in the scaleup domain as a
[01:51] we have in the scaleup domain as a function of time.
[01:54] So initially we had a few tens going up to 64 by 2022.
[01:58] Um it has then stalled largely for about
[02:00] 4 years. Uh main reason for that is
[02:03] 4 years.
[02:03] Uh main reason for that is because of the amount of GPUs that you can install in a single rack and because your constraint to a single rack in terms of copper based interconnect the reach is simple simply not long enough to go beyond a single single rack.
[02:19] But of course more recently we have seen announcements from Nvidia that they are continuing to scale the scaleup domain um to something like 576 or maybe even a thousand GPUs very soon.
[02:32] Now um and one of the reasons is that they were able to uh increase the power footprint purely the the um the consumption of a single rack um to something like 600 kilowatt.
[02:44] Um we know that UA link has at least logic capability to support up to a,000 GPUs in a scaleup domain.
[02:54] Um so the question is can we scale this up to maybe 10,000 and if you look for example at at Google that's the super pot they're already getting quite close to that.
[03:02] So to understand what that
[03:04] that.
[03:08] So to understand what that actually means in terms of uh GPUs and actually means in terms of uh GPUs and the connectivity and the real scallop.
[03:10] the connectivity and the real scallop interface that you would have there um.
[03:12] interface that you would have there um for the second half of 2026 we will have.
[03:15] for the second half of 2026 we will have GPUs that um will have a scalup.
[03:18] GPUs that um will have a scalup interface 14.4 4 terabit per second.
[03:21] interface 14.4 4 terabit per second coming in and also going out of the chip.
[03:24] coming in and also going out of the chip um over a over a single uh edge of the.
[03:27] um over a over a single uh edge of the shoreline.
[03:31] shoreline. So 25 mm uh the GPU power for such a device is roughly today on the.
[03:33] such a device is roughly today on the order of a kilowatt.
[03:36] Um and the order of a kilowatt.
[03:37] Um and the shoreline density that you would end up with for the scalup interface is 6 terab.
[03:40] shoreline density that you would end up with for the scalup interface is 6 terab per second per millimeter.
[03:42] per second per millimeter. And it's actually quite interesting to see how.
[03:45] And it's actually quite interesting to see how this could end up like uh for example.
[03:47] this could end up like uh for example 2032 5 to 6 years from now if we assume.
[03:51] 2032 5 to 6 years from now if we assume that we would be able to succeed to.
[03:53] that we would be able to succeed to increase the shoreline density from 6.
[03:55] increase the shoreline density from 6 terab per second per millimeter today to.
[03:58] terab per second per millimeter today to a technology that would support 10.
[04:00] a technology that would support 10 terabit per second per millimeter.
[04:03] Um then we would be able to have a scalup
[04:05] then we would be able to have a scalup interface with an IO capacity of 250.
[04:08] interface with an IO capacity of 250 terab per second per millimeter.
[04:11] the GPU power uh footprint would be 3 kilowatt.
[04:14] power uh footprint would be 3 kilowatt hours purely the compute itself.
[04:17] hours purely the compute itself.
[04:19] Um and of course to be able to dissipate that amount of power you do need advanced cooling solutions uh to remove the heat.
[04:24] advanced cooling solutions uh to remove the heat.
[04:26] And the question is can we do this through co- package optics?
[04:30] Nvidia has announced that they will run optical scale up uh through CPU solution.
[04:32] scale up uh through CPU solution.
[04:35] So it's interesting to project whether that actually will work for um this generation that I showed you 2032.
[04:36] it's interesting to project whether that actually will work for um this generation that I showed you 2032.
[04:39] So cool packaged optics today um many technologies in play.
[04:42] cool packaged optics today um many technologies in play.
[04:45] I'm just going to show you some of the underlying optics that could be used.
[04:46] show you some of the underlying optics that could be used.
[04:48] Um today it's 200G per lane but we do need to move on and go towards 400 gig per lane co- packaged optics.
[04:51] per lane but we do need to move on and go towards 400 gig per lane co- packaged optics.
[04:54] So some of the interesting optical devices that you can use uh and Adamic is working hard on to uh to optimize is a Cband transcal detector.
[04:56] optics. So some of the interesting optical devices that you can use uh and Adamic is working hard on to uh to optimize is a Cband transcal detector.
[04:59] optical devices that you can use uh and Adamic is working hard on to uh to optimize is a Cband transcal detector.
[05:01] Adamic is working hard on to uh to optimize is a Cband transcal detector.
[05:03] Adamic is working hard on to uh to optimize is a Cband transcal detector.
[05:06] optimize is a Cband transcal detector absorption modulator um is a picoscond absorption modulator um is a picoscond effect.
[05:12] So this device has extremely high bandwidth.
[05:14] We've shown that it has far beyond 100 GHz of electrooptical bandwidth.
[05:21] Um the device that you see here is a silicon tacted germanmanium silicon device with a lateral PIN diode.
[05:26] uh we do have some silicon that we have in the germanmanium to move the uh bandage towards the sea pant and it's very compact 10 by 15 square micron approximately which is of course is important to get to these very high shoreline densities.
[05:41] we've shown um such device at the wafer level uh with reasonably low transmitter penalties extinction ratios something like 3 4 dB so it's sufficient for uh scale up uh applications.
[05:57] um we're working to continue to optimize the device.
[05:59] Uh today we're running it on in our pilot line on 300 mm.
[06:02] Uh the main focus is to reduce wafer level
[06:07] focus is to reduce wafer level variability.
[06:10] Uh so to further optimize the the process conditions.
[06:12] the the process conditions.
[06:15] We've shown that it can work at uh 400 gig per lane uh net uh data rate.
[06:19] gig per lane uh net uh data rate.
[06:21] Uh so you can see some of the eye diagrams here.
[06:23] So the most relevant ones are of course 212.5 GB because that gives uh or takes into account the overhead that you need for the uh the forward error correction.
[06:27] course 212.5 GB because that gives uh or takes into account the overhead that you need for the uh the forward error correction.
[06:29] takes into account the overhead that you need for the uh the forward error correction.
[06:30] need for the uh the forward error correction.
[06:32] The eyes don't look really good.
[06:36] Uh granted but the limitation actually is not because of the EM.
[06:39] The limitation is really because of the arbitrary waveform generator instrument that we are using.
[06:41] limitation is really because of the arbitrary waveform generator instrument that we are using.
[06:43] arbitrary waveform generator instrument that we are using.
[06:46] Um you can see this in the measured uh frequency response that you can see here.
[06:48] in the measured uh frequency response that you can see here.
[06:51] um electrical backto back was me measured which is the blue curve and then we also measured the um uh entire link with the electro absorption modulator and you can see that at around 100 GHz um we have 20 dB of loss already um but most of that loss
[06:54] blue curve and then we also measured the um uh entire link with the electro absorption modulator and you can see that at around 100 GHz um we have 20 dB of loss already um but most of that loss
[06:57] um uh entire link with the electro absorption modulator and you can see that at around 100 GHz um we have 20 dB of loss already um but most of that loss
[07:00] absorption modulator and you can see that at around 100 GHz um we have 20 dB of loss already um but most of that loss
[07:02] that at around 100 GHz um we have 20 dB of loss already um but most of that loss
[07:06] at around 100 GHz um we have 20 dB of loss already um but most of that loss
[07:09] of loss already um but most of that loss is actually coming from the instruments.
[07:13] is actually coming from the instruments that we used not from the device so it actually shows that uh the device indeed has that very high bandwidth that we also measured.
[07:20] also measured Um we also need photo detectors of course.
[07:24] So here we have different options. We're working on germanmanium pin devices.
[07:32] Um we've also shown at last OFC just passed Germanmanium APD devices.
[07:38] Uh both which have bandwidths for the pin beyond 100 GHz far beyond I can't say I will show on the next slide.
[07:43] Um for the APD at a moderate gain of around two uh so effective responsivity 1.8 data amps per watt.
[07:51] We have something again of on the order of 80 GHz today.
[07:56] So you can see the um electrooptical response of the pin detector.
[08:01] Uh as soon as you bias it sufficiently, we easily have beyond 100 GHz of 3dB bandwidth.
[08:07] Um and we also have very high responsivity in the in the C band.
[08:09] This device also has extremely low capacitors.
[08:11] extremely low capacitors.
[08:14] Um you can see here the uh characteristics from the APD itself.
[08:17] Um and again as mentioned very high bandwidth.
[08:19] Now the question of course can we use that technology for the um uh CPU?
[08:24] The answer is no.
[08:28] Uh CPU typically consumes still something like four to five pjles per bit which means you would end up with 1.25 kW for the optics alone which is simply not possible.
[08:36] You can't dissipate that amount of power.
[08:38] So the solution that we're focusing on is to go from fast and narrow to a wide and slow approach uh in a number of steps.
[08:45] We first select a very simple modulation format non- returnturn to zero.
[08:49] We choose it sufficiently low so that you can get rid of this uh DSP that you need uh which reduces power consumption significantly.
[09:01] Um,
[09:03] we then of course need to recover the amount of data or the data capacity, the bandwidth that we lose by going from fast and narrow to wide and slow.
[09:12] fast and narrow to wide and slow.
[09:12] And the way we do that is in two steps.
[09:13] We the way we do that is in two steps.
[09:13] We move the optical engine onto silicon interposer for example where you can have much uh finer pitch connectivity between XPU and the CPU module.
[09:16] move the optical engine onto silicon interposer for example where you can
[09:17] interposer for example where you can have much uh finer pitch connectivity
[09:20] have much uh finer pitch connectivity between XPU and the CPU module.
[09:23] between XPU and the CPU module.
[09:23] And we use dense wavelength division multiplex in 32 wavelengths or 64 wavelength.
[09:25] use dense wavelength division multiplex in 32 wavelengths or 64 wavelength.
[09:29] The devices that we develop for that um way of working are very compact.
[09:31] devices that we develop for that um way of working are very compact.
[09:33] Uh this is an example of a disk modulator.
[09:37] an example of a disk modulator.
[09:37] Um why disk modulator?
[09:39] disk modulator? We need a very small ring to have a a large uh FSR.
[09:43] ring to have a a large uh FSR.
[09:43] Um and in the end it collapses.
[09:45] the end it collapses.
[09:45] Eventually the the micro ring collapses down into a disk.
[09:47] micro ring collapses down into a disk.
[09:47] So we've shown one which has 6.4 terz of of FSR.
[09:51] So we've shown one which has 6.4 terz of of FSR.
[09:55] Um you don't need to optimize for very high bandwidth anymore.
[09:57] for very high bandwidth anymore.
[09:57] uh modulation bandwidth of the device that we have is 26 to 30 GHz where you do need to optimize it very strongly to have a very low or very good transmitter penalty.
[09:59] modulation bandwidth of the device that we have is 26 to 30 GHz where you do
[10:02] we have is 26 to 30 GHz where you do need to optimize it very strongly to
[10:04] need to optimize it very strongly to have a very low or very good transmitter penalty.
[10:07] have a very low or very good transmitter penalty.
[10:07] You need the DWDM filters uh for supporting those many wavelengths.
[10:11] penalty. You need the DWDM filters uh for supporting those many wavelengths.
[10:13] for supporting those many wavelengths.
[10:16] So this is one example where we actually leverage the fact that we do the uh lithography on our 300 mm line.
[10:21] It's immersion lithography.
[10:23] So we can define very well the uh filter structures that we use.
[10:28] Uh so you can see the response of this 32 wavelength uh filter it is very uniform across the entire band.
[10:35] Um the other uh technology piece that we are leveraging for this um uh wafer level or for these uh wide and slow approach is hybrid bonding.
[10:45] And one of the reasons why we do that is it allows us to have a very low capacitive interface between the photo detector and the trans impedance amplifier the electronics that improves SNR.
[10:56] So you need less laser power to close the link and again you reduce the overall power that you need to uh close the link.
[11:02] So what we project is that we can close such a link with two pico juice per bit and a density of 2 terabit per second per millimeter.
[11:11] That then gets you something like to like 500 watt for the optics.
[11:13] Uh still
[11:16] like 500 watt for the optics.
[11:16] Uh still not great.
[11:18] So we are working also on other solutions uh by moving for example the active pick in the same stack as the XPU uh onto an optical interconnect wafer.
[11:28] uh the optical interconnect wafer is purely passive and can be used with silicon nitride waveguides to move data between XPS sitting on one end of the wafer and the other end.
[11:38] So this is an example where we hybrid bonded uh picss onto such passive optical interposer wafer um and where we actually uh measured a stitched silicon nitride wave guide with very uh good losses.
[11:49] Uh we've also shown the eancent couplers between the affective pick and the underlying um optical interposer to have very low loss.
[12:00] We need even better modulators to drive the power uh even lower.
[12:05] I will not say too much about this but we are working very intensively at IMC to integrate 35 into the front end of our uh silicon photonics process and this would allow us to build a Cisco modulator at wafer
[12:18] us to build a Cisco modulator at wafer scale which today has not yet been shown.
[12:20] scale which today has not yet been shown uh with very good VPIL numbers and very low losses.
[12:23] uh with very good VPIL numbers and very low losses.
[12:27] low losses. There's also other options uh BTO being one of them.
[12:29] uh BTO being one of them. For example, uh which is another material that we're working on to integrate uh with a collaboration that we have at with VCO.
[12:31] uh which is another material that we're working on to integrate uh with a collaboration that we have at with VCO.
[12:33] working on to integrate uh with a collaboration that we have at with VCO to grow BTU on 300 mm.
[12:35] collaboration that we have at with VCO to grow BTU on 300 mm.
[12:38] to grow BTU on 300 mm. It's again one option to um integrate an loss modulator onto uh our silicon photonic platform.
[12:43] option to um integrate an loss modulator onto uh our silicon photonic platform.
[12:46] onto uh our silicon photonic platform. And in the end where where you could end up with is this kind of vision uh 3D optical interconnect.
[12:48] And in the end where where you could end up with is this kind of vision uh 3D optical interconnect.
[12:50] up with is this kind of vision uh 3D optical interconnect. You integrate, for example, up to 16 of those GPUs onto a wafer uh with an optical switch, which the HBM included, the CPUs, the network processors, the lasers we're also working on there.
[12:52] optical interconnect. You integrate, for example, up to 16 of those GPUs onto a wafer uh with an optical switch, which the HBM included, the CPUs, the network processors, the lasers we're also working on there.
[12:56] example, up to 16 of those GPUs onto a wafer uh with an optical switch, which the HBM included, the CPUs, the network processors, the lasers we're also working on there.
[12:58] wafer uh with an optical switch, which the HBM included, the CPUs, the network processors, the lasers we're also working on there.
[13:01] the HBM included, the CPUs, the network processors, the lasers we're also working on there.
[13:03] processors, the lasers we're also working on there. Um, and could be used as a means to drive down power further.
[13:06] working on there. Um, and could be used as a means to drive down power further.
[13:09] as a means to drive down power further. The challenges with this wafer scale approach are very big, right?
[13:10] The challenges with this wafer scale approach are very big, right? I mean, I'm just going to name one of them.
[13:12] approach are very big, right? I mean, I'm just going to name one of them. Uh, the the power that you would dissipate on this type of wafer would be something
[13:15] I'm just going to name one of them. Uh, the the power that you would dissipate on this type of wafer would be something
[13:17] the the power that you would dissipate on this type of wafer would be something
[13:18] on this type of wafer would be something like 50 kilowatt.
[13:21] Uh so imagine how you need to remove the heat out of that uh of that wine food.
[13:23] Okay, thanks a lot for your uh attention.
[13:26] Any questions?
[13:29] Be happy to answer questions.
[13:47] So with this wave for scale approach, you talked a lot about power.
[13:49] Uh what about latency of the with you know like with a wide and slow is there a big latency advantage in the electrical optical conversion versus for example the traditional narrow and high speed?
[13:51] Yeah, it's a good question.
[13:54] um you somehow remove part of the multiplexer or the serialization latency and even more important um the wide and slow approach runs at a much lower uh bitter rate.
[13:55] So you can get rid of the latency
[14:20] rate.
[14:20] So you can get rid of the latency introduced by the forward error correcting schemes and also the power associated to that.
[14:26] So also wide and slow will help with with latency.
[14:30] Um and then if you looked carefully at the wafer scale picture that I showed you, there's actually an optical circuit switch in the middle of that.
[14:37] Uh so one other way we are working on to remove latency from the fabric is by looking at or exploring whether it makes sense to use an optical circuit switch in the scaleup domain rather than these electrical packet switches that you would have today.
[14:50] >> And and what sort of uh reconfiguration time are you looking at for that op that that circuit switch is the obvious question.
[14:56] It's a yeah a good question.
[14:59] Uh there's two sides to that.
[15:01] There's purely the uh speed of the switching elements themselves.
[15:08] Um if it's thermoptic then it's going to be reasonably slow microscond scale.
[15:09] With the BTO can be far faster uh nancond scale.
[15:15] But that's not the only problem that you need to solve.
[15:17] You also need to think about how the control plane will
[15:21] think about how the control plane will need to function to configure your.
[15:23] need to function to configure your optical circuit switch uh from the um optical circuit switch uh from the um application point of view.
[15:28] So to have a a good answer to that question, you need to consider both of these uh these aspects.
[15:33] aspects.
[15:36] Yeah, that makes sense. Thanks.
[15:37] Yeah.
[15:42] For the uh 35 on silicon moscap modulators you showed wer scale.
[15:45] modulators you showed wer scale.
[15:47] Yeah. Yeah.
[15:47] Do you have any data on the uh cut off frequency yet?
[15:49] frequency yet?
[15:51] No. Um it's meant for wide and slow initially for sure.
[15:55] Um so that's our main target uh today.
[15:57] So again we we would be targeting electrooptical bandwidths in the region of 10 to 20 GHz.
[16:00] would be targeting electrooptical bandwidths in the region of 10 to 20 GHz.
[16:02] We don't need really much more for a wide and slow and and and really focusing today on getting the losses as low as possible and the VPL product uh as low as possible.
[16:05] GHz. We don't need really much more for a wide and slow and and and really focusing today on getting the losses as low as possible and the VPL product uh as low as possible.
[16:07] that will be the main target for now and that we're focusing on.
[16:08] focusing on.
[16:11] Thank you.
[16:26] Thank you for your talk.
[16:27] Could you elaborate for the SEC as catap modulator?
[16:31] Yeah.
[16:31] Yeah.
[16:34] I will not say too much about it just yet.
[16:38] Um the challenge that we are trying to overcome is introducing 35 material in the front end of a silicon foundry.
[16:46] Uh which is for sure not an easy thing to do.
[16:49] Um we are looking at to do that at wafer scale.
[16:55] Um we have an approach uh to to indeed move or or integrate 35 onto our silicon wafers.
[17:03] Um the other challenge that we need to overcome is we cannot have any gold in such a silicon foundary.
[17:10] So we need to come up with a way to make very good contacts uh to that device.
[17:15] That's what we have shown today already.
[17:17] You saw the the the picture.
[17:20] So still today it's very much an uh integration effort that we are working on.
[17:27] So maybe you are talking about the 358 new passport and um like a micro new passport and um like a micro transfer printing to employ it.
[17:32] Yeah, it this what we're using is non microtransfer printing.
[17:36] We're integrating it much deeper into the front end.
[17:41] Um microtransfer printing works, but here we think we need another approach because um imagine uh a wide and slow optical transceiver that may have uh tens or even hundreds of modulators.
[17:54] then some you may want to use something that's uh even more reliable and has even better manufacturability compared to uh transfer printing.
[18:06] Okay.
[18:07] Okay.
[18:13] Thank you.
[18:25] Um, oh yes, please. 14.
[18:25] So yeah, my question would be around u
[18:27] So yeah, my question would be around u if you could provide like some insights.
[18:32] around substrate packaging versus interposer level uh packaging and die to die interconnects.
[18:37] what are the main gaps to re that you know the main challenges you see moving to the interposer level uh interconnect in your opinion from a manufacturability packaging perspective.
[18:47] Yeah.
[18:49] Uh good question.
[18:52] Um it's mainly about um so especially what uh what we are exploring at Adamec is um this this way of um assembling uh on a on a wafer um massive uh of very high shoreline density.
[19:11] So then what you need to do is in a manufacturable manufacturable way scale the pitches of the interconnect the electrical interconnect to very low uh pitches.
[19:22] Uh if you look at today a UCI uh typically has like a 45 micron pitch between the
[19:28] has like a 45 micron pitch between the microbumps to get to your 10 terabits.
[19:31] microbumps to get to your 10 terabits per second per millimeter.
[19:33] per second per millimeter. If you want to scale that uh even higher um and you
[19:37] to scale that uh even higher um and you want to do that from an optical
[19:39] want to do that from an optical perspective, you need to come up with um
[19:42] perspective, you need to come up with um firstly photonix devices that have
[19:45] firstly photonix devices that have sufficient small footprint to match such
[19:47] sufficient small footprint to match such a 40 micron pitch which is not an easy
[19:50] a 40 micron pitch which is not an easy thing to do or you need to think very
[19:52] thing to do or you need to think very carefully how you floor plan your
[19:54] carefully how you floor plan your devices. Um
[19:57] devices. Um and then of course also it's about uh
[20:00] and then of course also it's about uh reliability and having high yield of
[20:03] reliability and having high yield of that interconnect when you do hybrid
[20:05] that interconnect when you do hybrid bonding. Again that is a significant
[20:07] bonding. Again that is a significant challenge that um that you need to
[20:09] challenge that um that you need to address. Uh so it's about um
[20:14] address. Uh so it's about um to us mainly uh further improving the m
[20:18] to us mainly uh further improving the m the yield and the maturity of the hybrid
[20:20] the yield and the maturity of the hybrid bonding process with very low pitches
[20:23] bonding process with very low pitches between your um your interconnect. Um
[20:27] between your um your interconnect. Um one my time is up apparently. Um I think
[20:31] one my time is up apparently. Um I think maybe just one one final note if I may.
[20:34] maybe just one one final note if I may. um hybrid bonding today is is uh is is
[20:38] um hybrid bonding today is is uh is is already used uh and has been
[20:40] already used uh and has been demonstrated with very small pitches um
[20:43] demonstrated with very small pitches um at a micron level for pure electrical
[20:46] at a micron level for pure electrical interconnect. One of the challenges that
[20:48] interconnect. One of the challenges that we need to address when you're starting
[20:49] we need to address when you're starting to use that for optics is that you will
[20:52] to use that for optics is that you will have um areas on your devices that have
[20:55] have um areas on your devices that have less um metal density let's call it that
[20:58] less um metal density let's call it that way. So it means that uh CMP and
[21:01] way. So it means that uh CMP and planerization steps are getting more
[21:03] planerization steps are getting more difficult. So it's that level of process
[21:05] difficult. So it's that level of process control that you need to to work on to
[21:07] control that you need to to work on to get a um a manufacturing process with
[21:10] get a um a manufacturing process with with high yield. So these in my mind are
[21:13] with high yield. So these in my mind are are the main challenges that we need to
[21:15] are the main challenges that we need to overcome.
[21:16] overcome. >> Okay, let's thank our speakers.