Towards wafer-scale optical interconnect relying on Silicon Photonics and advanced 3D assembly

https://www.youtube.com/watch?v=spPFSk1ycO4

Summary

TL;DR — This presentation explores the integration of silicon photonics and advanced 3D assembly to create wafer-scale optical interconnects, crucial for scaling AI compute infrastructure. The talk highlights the limitations of current copper-based interconnects for large-scale GPU clusters and proposes solutions involving co-packaged optics and advanced modulation techniques to achieve higher bandwidth and lower power consumption.

Key points

• Current AI compute infrastructure relies on GPUs with HBM and IO chiplets, facing limitations in scale-up networks due to copper interconnect reach and power constraints.

• Future AI systems will require significantly higher bandwidth (e.g., 14.4 Tb/s per GPU interface by 2026) and higher shoreline density, pushing the need for optical solutions.

• Silicon photonics, particularly C-band electro-absorption modulators and germanium photodetectors, are being developed for high-speed (400 Gb/s per lane) co-packaged optics.

• A "wide and slow" approach using non-return-to-zero modulation, silicon interposers, and dense wavelength division multiplexing (DWDM) is proposed to reduce power consumption and DSP overhead.

• Advanced assembly techniques like hybrid bonding and wafer-level integration of optical components are key to achieving high-density, low-power optical interconnects.

• Emerging technologies like 3D integration and novel materials (e.g., BTO) are being explored for future wafer-scale optical interconnects to further reduce power and latency.

Takeaway — Advancements in silicon photonics and 3D assembly are essential for overcoming the limitations of current interconnect technologies and enabling the continued scaling of AI compute infrastructure.