# INTEL KEYNOTE: Advanced packaging as the critical enabler. WHAT ARE THE SUCCESS FACTORS?

https://www.youtube.com/watch?v=3jXcWmsaN3s

[00:00] This is one of the success stories of the European industry and why we are here.
[00:04] In the last years, we have seen a company called Optoscribe being able not only to introduce a technology but also to make sure that this is scalable by being acquired by one of the leading companies in the semiconductor industry worldwide.
[00:17] I am happy to know Nick Sila for for many years in many different contexts with many different companies and he always told me the whole success here is not just what we can do but who can make others do something that they haven't done before.
[00:35] Today Nick Sila has moved to the US.
[00:38] He's one of the key people in Intel making co-package optics a reality and offering the Intel technology to all of you.
[00:45] It is our honor and pleasure to welcome one of us as the keynote of this year's government meeting.
[00:49] Nick Sila, thank you for coming to Brussels.
[00:54] The floor is yours.
[00:58] [applause]
[00:59] But yeah, thank you very much for the
[01:00] invitation to give the keynote talk today.
[01:02] Um, what I'm going to really talk today is about how we go about scaling co-ackaged optics.
[01:06] So I'm going to talk generally about some of the challenges that are there in the industry what we need to the kind of areas we need to solve and we need to put put a lot of effort into and then to give you a bit of an idea of what are doing.
[01:16] I'll also thank Luron for the the introductory talk earlier his gave a great great keynote earlier.
[01:22] A lot of the concepts that Luron talked about I'll also cover as well.
[01:26] So thank you for introducing some of those aspects.
[01:30] Okay.
[01:33] So, starting with the challenge, right?
[01:33] Uh I think we as we all heard AI compute has has has grown dramatically over the past uh decade or so.
[01:42] And the one of the key challenges as as as has been mentioned multiple times already is that the the memory bandwidth and the IO bandwidth have have not kept up with the growth in compute.
[01:52] Right?
[01:54] So this is creating a what what's been called the the memory wall, but I would also say it applies even more so to the IO aspect.
[02:01] here.
[02:03] As we build and scale these systems, they're becoming dramatically IO IO limited.
[02:05] So particularly when we look at um the the kind of workloads for for AI both training and inference, they they have the same bottleneck IO and different stages of the the uh inference and and reasoning uh processes, they have different stage specific uh bottlenecks there.
[02:21] um and which stress different subsystems.
[02:24] So there are situations where data is suddenly needs to be shuttled back between multiple different GPUs and at that point you know IO is is becomes a key bottleneck.
[02:33] So making sure we we we're able to keep the IO and the compute in in lock step that's where we we need to focus on in order to uh to continue to allow these systems to scale.
[02:43] Okay.
[02:48] So really right now the the the key challenge to scaling uh AI systems really comes down to bandwidth density and efficiency of the IO itself.
[02:55] Okay.
[02:58] So when we look at the the network and and again Luron went through this in
[03:02] Some detail earlier.
[03:04] Um right now we have these several different domains of networking.
[03:06] Um and I'm going to focus particularly on the scale up which I think as again as was pointed out earlier is going to be one of the biggest challenges for integrating and scaling uh CPO.
[03:16] Okay.
[03:20] So when when we look at the domain size um that's directly affecting um the the system performance um the the larger we can make those domains the larger we can um to make the the those numbers of links between XPUs in a in the domain in the in the scale up domain um will will drive drive ultimately the performance of the systems and when we look at what copper can deliver um as as no doubt some of you have seen seen you know OFC this here.
[03:48] You know, copper is starting to get starting to run into to to significant challenges as we we we uh we raise the speeds there.
[03:54] There are some mitigation routes that copper is trying to eek out to get a bit further.
[03:58] You know, active copper, for example, but still fundamentally that's going to add
[04:03] extra extra power consumption and still
[04:05] limited reach ultimately. We want to we
[04:07] want to be able to scale up these
[04:08] systems. And so, one of the things that
[04:10] optics brings is it it will enable scale
[04:12] up domains to no longer be limited by by
[04:16] copper reach. Okay. And so so so we we
[04:19] see this as a key key approach going as
[04:21] forwards. Now the the when CPO will be
[04:24] adopted there'll be you know earlier
[04:25] examples. So for example you know Nvidia
[04:27] showed in in in in the in the scale out
[04:29] domain but I think that the there's
[04:32] there's a a significant demand from from
[04:34] from the end users out there to start to
[04:37] deploy CPO systems even in the scale
[04:39] even in the scale up network. So that's
[04:41] being worked on right now and and uh the
[04:44] systems will be will be deployed in in
[04:46] the not too distant future. Where we see
[04:48] is is CPO being complimentary to copper
[04:52] um and really uh providing this a
[04:55] transition to to ultimately the the
[04:57] whole system moving moving to to to
[04:59] optical eventually but there'll be a
[05:01] gradual transition.
[05:04] Now looking at the the demand requirements I think you know a lot of you are you know exposed to the the supply chain demands which we're seeing from the the uh the customer side at the moment.
[05:15] you know we we we've uh we've seen and we saw a really interesting talk by Andy Betostein at the optica executive forum.
[05:22] for those of you who are there you know again we're seeing um the the demand for the number of optical links in next generation data centers being really staggering.
[05:33] I mean, so so if we introduce optics into the the scale up network space,
[05:41] um Andy was projecting more than 100 million600G equivalents in a in a 1 gigawatt data center, right?
[05:48] And if we look uh at the the data center buildout, at least there are at least five 1 gigawatt data centers expected to come online this year and then a continued exponential growth for the rest of the decade, right?
[06:03] So it only takes a few of those to start adopting CPO for the
[06:06] volume requirements to to really skyrocket and go through the roof.
[06:10] So I think one of the key things I'd like to say to to the industry and to you all that we need to get start getting ready for for for this ramp right now.
[06:17] So this this affects the entire supply chain affects you know component supply right the way down to picks and activives and FAUs but also assembly capacity packaging capacity as a whole.
[06:29] you know, we're seeing really really uh stark demand numbers from from our from our customers that we're having to start to to to uh to build out and prepare for in the in the in the near future.
[06:38] So, uh I think you know all of this trickles down all the way down to to metrology equipment.
[06:45] So, for example, um test assembly mrology capabilities is that the entire supply chain is going to be really really strained just by this this one particular application.
[06:55] Okay.
[06:57] So my message here is significant volume in investment is required now really to to get ready for this.
[07:03] Okay.
[07:03] Coming back to what I'm really going to talk about here is is how advanced
[07:07] packaging can can really can really help.
[07:09] here and and advanced packaging has become uh one of the key uh scaling vectors for for for packaging for for for compute as a whole.
[07:18] the fact that, you know, you you're you're reticle limited with a with a with with a single die.
[07:25] And so it by nature you need to go to multi-d packages in order to continue to scale the performance of the of of the overall package.
[07:31] And so you can see we're we're in an era where we have heterogeneous integration.
[07:35] We have lots of different chiplets that are specialized in doing individual tasks.
[07:41] So HBM, IO die, compute die and and various different dialect which are built up and stacked in 3D.
[07:47] Okay.
[07:49] So there may be a base down underneath.
[07:51] There's now maybe a compute die placed on top of that.
[07:53] And and it's really built up in a in a in a a really large die complex.
[07:58] And this is this is where we are right now.
[08:01] And so we've really got to think that CPO's CPO has to fit into this ecosystem.
[08:04] CPO has to be part of this.
[08:07] And also it provides some advantages as
[08:09] Well. Okay.
[08:12] So when we look at what's what advanced packaging brings to a conventional electronics package, it brings lower power consumption because your you know your your trace lengths much shorter, your bump gives much greater density because you have much smaller bump pitches, much smaller bumps and you're able to stack stack in 3D.
[08:28] Okay.
[08:30] So so when we bring that towards CPO, um you know this this this enables us to leverage the same those same advantages.
[08:35] So this enables us to drive down the power consumption.
[08:39] Um it gives us increased bandwidth, better thermal management.
[08:42] This is really important.
[08:44] You get better you get um better thermal transfer by having you know these architectures where you can really put a a cold plate directly on top of this entire stack.
[08:51] Take the heat away [snorts] and then uh reduce signal pass because you're stacking in 3D.
[08:55] You're not having to go as far with your signal lengths, right?
[08:59] So all of these same things uh apply to to to CPO integration.
[09:03] So one of the key caveats though is that in order to do that you need to really essentially adopt electronic style manufacturing and assembly for CPO.
[09:11] Okay.
[09:14] So this is it needs you need to transfer the the assembly processes and mindset that photonix has really taken and just you needs to needs to be taken into this in into this domain and that that means some changes because you know a lot just you know frankly speaking phonics for the for for so long has often used kind of exot some exotic and artisan assembly processes and things like that and we need to make sure that we are we we become compatible compible with with conventional high volume electronics manufacturing.
[09:46] and then we look at package sizes I mean these are some examples here so where we are right now it's an example gardify it's a multi multi-chip package there even in the short term package sizes are growing dramatically I mean right now we're we're seeing near future scaling to 10 10x reticle and beyond in a single package and purely electrical case but then we need to bring a CPO into that as well So package sizes are scaling
[10:12] dramatically.
[10:14] and then bringing CPO into to this this ecosystem is what is it it as I mentioned the CPO generally and optics in gerally typically uses a lot of non-standard processes compared to a typical assembly flow in electronics.
[10:28] So we need to work hard to to to to drive those processes to be compatible.
[10:34] So if I give some examples here, you know, I've said here high throughput passive or vision based alignment, right?
[10:39] Right now active alignment, okay, it's kind of a necessary evil, it's kind of allowing you to accommodate some of the manufacturing process variability in some of the components.
[10:52] My argument is longer term, we want to try and move away from that.
[10:53] We want to try and make it look like an electronics assembly flow.
[10:58] Okay, but right now it's, as I said, necessary evil.
[11:01] um wafer level assembly cru crucial that's done now routinely for all the 3D advanced packaging and 2.5D advanced packaging um we need we just need to adopt that doing
[11:14] die level package level assembly of individual dies is is is not fast enough.
[11:19] wafer level test again really important.
[11:20] we saw some of that earlier as well you can see some of some some of the high volume uh um test equipment who we got here.
[11:26] so this is a a high that's that's actually an end ofline package tester a fully automated uh CPO package tester a unit that's that's uh that's runs at high volume.
[11:34] And then we we also need to to be cognizant that the reliability standards are typically different in a semiconductor package than they are in in uh in optics.
[11:44] Okay.
[11:44] So coming from the telecoms and andcoms where you you've maybe got teleordia type standing standards in this case you need to go to JDE right and so that that introduces some additional challenges.
[11:58] So for example, damp heat for example in JDC is is actually uh 105 degrees 85% humidity instead of 85 85.
[12:08] So that puts an additional level of stress on the on the components that they have to hit and there are a bunch of others as well.
[12:14] detachable connectors.
[12:16] I know there's a whole session on this uh next super important.
[12:18] I think this is something that's some people have overlooked, but actually being able to have a a package that's fully known good and testable at every single stage of that assembly is super important.
[12:30] So when you're doing optical attach typically that's the last stage of the assembly flow.
[12:35] Okay.
[12:38] So at that point if you have a yield failure the whole package is essentially gone with all the expensive silicon.
[12:45] So, you know, a a few bucks on a on a on an FAU can can ruin an entire package.
[12:51] Okay.
[12:51] So, having a detachable connector solution really allows you to have that testability before you commit that to the package and that means you get much better yields overall.
[12:58] And then, you know, obviously this the standard things you would expect from from from assembly.
[13:03] So, reflow compatibility also TCB is is used often.
[13:05] That's another important one that you have to bear in mind.
[13:10] So the temperatures in TCB can be can be higher than than solder refflow
[13:15] but generally very locally but you know.
[13:18] that can affect some some of the the thermal uh profiles that some of the components have to see during the assembly flow.
[13:23] And then the final one is on architectures.
[13:26] I know so so Intel Foundry is is kind of agnostic to the particular type of silicon coming in.
[13:31] So we we work with a lot of different architectures.
[13:35] Now there's there's there's still quite a lot of different uh configurations out there on the market.
[13:41] I think there seems to be a gradual move towards uh a lot of people move adopting a thin pick with EIC on top configuration that has a lot of advantages but there are still some industry looking doing other different kinds of stacks as well.
[13:55] So um that's one thing to that uh that we have to be we have to be cognizant of and uh make sure we have the assembly processes to cope with that.
[14:03] So again key takeaway message here.
[14:06] So I think CPO is fundamentally a packaging challenge as much as a photonix challenge right.
[14:10] So it's it's this is these things are the key things that need to be uh need to be
[14:17] solved and worked on in order to take this to to to high volume production.
[14:21] Okay.
[14:23] So looking at what what Intel has as a as a spectrum of technologies.
[14:28] So you know we do everything from 2D packaging 2.5D for veros for us directors where we where we introduce hybrid bonding and beyond.
[14:37] And then we've got things like glass core and CPO which obviously we've been talking about and we'll we'll talk about in a bit more detail as well.
[14:44] So as I said you know we we we think CPO complements copper.
[14:47] um we'll use couple where it makes sense but but CPU really allows that that that short to long distance uh trans transition and allows us to do uh long distance uh uh low bandwidth high bandwidth uh low energy uh links as well.
[15:02] So then we we look at um a kind of interconnect pitch versus different kind of technology here.
[15:09] We we look at um kind of the first generation CPO where there's permanent fiber attaches.
[15:14] we we're kind of limited to
[15:17] The the fiber density at the the shoreline there.
[15:22] Okay. So, so that's where we're up at this kind of 250 or 127 micron pitch uh region.
[15:26] As we move to detachable connectors, we're able to get an increase in density there.
[15:31] Uh and then where we see there being a big step forward is going to to to vertical connectivity.
[15:35] I think again as Luron said earlier today, um that's that's a key area of technology that that that Intel are actively working on.
[15:43] So we have in this case vertical expanded beams with two dimensional arrays of of cores coming out of that.
[15:47] Um and that that we we think that's much more scalable.
[15:52] It's integrated into a 3D stack.
[15:53] So it means that the the the the entire package is is uh wafer level assembly compatible as well.
[16:01] And then longerterm where we see things really really taking off and we saw some of that from from Andrea Ephos uh in the last talk is moving into in package optical interconnects.
[16:11] And that's where we we actually see a longerterm view of of being able to construct and build extremely dense high perform high
[16:18] performance AI systems and I'll talk about that in the next few slides.
[16:20] Okay.
[16:23] So looking at glass core substrates.
[16:26] So you know this has been talked about in the industry for quite some time.
[16:27] You know organic substrates uh served us well and have you know indeed been able to scale to to even very large package sizes already.
[16:38] But fundamentally you're you assembling an organic substrate to to silicon chips on top which have a large CTE mismatch.
[16:47] Right?
[16:49] So that fundamentally creates some you know some some uh you know dimensional issues some warpage issues particularly as you start to scale the the size of the package up even larger.
[17:01] Now there there's been a lot that has been done on the organic side to try and tune that and try and compensate and and try and stretch that out a lot a lot further but ultimately we we think it's very much worthwhile just taking the shift and jumping to changing the substrate material itself completely and going to glass.
[17:15] Okay.
[17:18] So, Intel has done a lot of work in this
[17:19] area, has developed a a fully automated pilot production line to to to run glass core processes.
[17:28] And this gives us the ability to uh have a much larger form factor, much more mechanical stability for for integration and packaging.
[17:35] Uh then adds a bunch of advantages when it comes to things like high frequency uh signal integrity as well.
[17:43] And then uh then temperature temperature as well.
[17:45] Okay.
[17:47] So then when we look at some of some of the examples here, you can see these these images are from the the the pilot production line in in Chandler.
[17:57] And you can see um some images here on the on the lower left hand side.
[17:58] This is hot off the press.
[18:00] These were presented at ECTC last week by my colleagues.
[18:05] And you can see this is a latest uh example of of a cross-section here of a glass core substrate.
[18:10] You can see the TGVs there through the middle.
[18:11] And there's 12 layer RDL on the top and the bottom.
[18:16] And there's actually an E-IB embedded interconnect die which is just there
[18:21] below the below the surface there which has micro bumps and extremely dense pitch.
[18:25] So first first demonstration of a fully integrated uh 24 layer glass core substrate with EIB in embedded in that as well.
[18:33] So really all the ingredients are here all all the abilities here uh to to continue and to scale this technology.
[18:39] Okay. And then having a a glass as a as a core obviously then brings in brings in the option for for optics integration.
[18:47] Okay. So I can show you an example here.
[18:50] So this is these are um waveguides 3D waveguides um integrated and written integrated with through glassass v.
[18:58] So you can see some examples here.
[19:01] These these are wave guides running in between the v.
[19:04] You can see these are 3D wave guides rooting changing depth um going in between the TGV forest allowing this to to be rooted rooted around on the on the glass substrate.
[19:13] And you can see here this is an example 100 by 100 this but it it scales up to to 500 by 500 which is the standard glass panel size
[19:22] that we that we have in Intel.
[19:25] Okay.
[19:25] So again, this this is uh we we see this as offering a significant potential uh path to to very very high density scaling of of AI systems um particularly with with CPO and and I'll finish with this future vision slide which I first presented at PE last year, but this is a kind of vision of how we how we would see some something like this being constructed.
[19:48] Okay, so you'd have a whole bunch of different die complex die complexes assembled on this this entire one large large scale package with an optical connectivity matrix right the way through that which has both onboard optics and as well as connections out to the external world.
[20:08] Okay, so we think this will enable kind of die to die level bandwidth densities stretching from short distances up to up to long distance lengths uh using a single architecture.
[20:20] Um so this is where we this is where we
[20:23] think that the the the future is uh for
[20:25] for high density compute. Okay.
[20:29] Okay. Um so to summarize so as I
[20:32] mentioned so AI scaling is fundamentally
[20:35] IO limited right now. Um and we we
[20:39] firmly believe that CPO provides a a
[20:41] solid path to continue to extend beyond
[20:44] the limits of copper uh and grow those
[20:47] domain sizes of scale up networks.
[20:50] Also with advanced packaging is a
[20:52] critical enabler. So being able to
[20:54] integrate and use heterogeneous
[20:56] integration to to make more and more
[20:58] complex packages and continue to drive
[21:01] the performance forwards.
[21:04] Scaling CPO is going to require a huge
[21:06] amount of investment across the entire
[21:08] ecosystem across all aspects of the
[21:10] ecosystem. And then we finally think
[21:13] that Glass Core provides a a uh a really
[21:16] exciting opportunity to to integrate uh
[21:19] and scale the the AI systems as we as we
[21:22] want to grow from small packages uh all
[21:25] the way up to panel size compute. Okay.
[21:28] Thank you very much.
[21:29] >> Thank you very much, Anique. Amazing.
[21:32] [applause]
[21:35] re really great presentation. All of you
[21:37] were taking pictures. Me too. But uh
[21:40] you're going to get the slides at the
[21:41] end of the event. So don't worry. But if
[21:43] you see something interesting, you know,
[21:44] take a picture. It never hurts. What can
[21:46] you do for them and what can they do for
[21:48] you?
[21:49] >> Okay. Well, you know, this is an Intel
[21:51] Foundry presentation. We're
[21:52] fundamentally a a foundry, a very high
[21:55] volume foundry. Um so no we're open to
[21:58] exploring opportunities there in terms
[22:01] of what we can you know what you can do
[22:02] for us I think you know there's a lot of
[22:05] challenges need to be faced in here
[22:06] there's any anybody that has interesting
[22:08] technologies you know we're we're very
[22:10] open to and interested to hear about it
[22:11] you know we you know if there are better
[22:13] ways of doing things we are all ears
[22:17] >> great question any further questions yes
[22:20] Peter Kirk from IM
[22:23] >> it's not so much a question it's more
[22:25] directed to My fellow audience members,
[22:28] we started today by sort of complaining,
[22:31] "Oh, Phutonics is not going to make it.
[22:33] There is too much low volume and high
[22:35] mix and and here we have an industry
[22:37] asking for us to come with a solution.
[22:40] People rejoice. [laughter]
[22:43] >> Thank you, Peter.
[22:44] >> Absolutely. I would like to give a big
[22:46] round of applause to Nick Sila.
[22:48] [applause]
[22:50] [music]
[22:53] Who will turn precision into real volume
[22:56] faster? Optica [music] Gamma Brussels
[23:00] 2026.
[23:01] This is where optics meets reality. Who
[23:04] [music] will scale? Who will deliver?
[23:08] Who will lead when the easy answers
[23:10] disappear?
[23:12] Optic [music] of gamma Brussels 2026.
[23:16] This is where the next phase starts.
[23:19] [music]