HUAWEI Tau (τ) Scaling Law Livestream

Key Takeaways

• The evolution of semiconductor technology is shifting from geometrical scaling to time scaling (tau) as the primary driver for performance gains.
• Time scaling focuses on optimizing signal propagation time (RC product) across devices, circuits, and systems, rather than just shrinking physical dimensions.
• At the device level, innovations like high-k metal gate and strained silicon improve performance by optimizing the RC product, contributing to time scaling.
• Circuit-level time scaling involves reducing logical depths and optimizing interconnects to shorten signal propagation delays between sequential elements.
• System-level evolution relies on architectural innovation and optimization, enabled by advancements in devices and processes, to achieve time scaling benefits.
• Logical folding is a new design methodology that optimizes digital circuits and systems across vertically stacked active tiers to shorten propagation time.
• Logical folding achieves significant improvements in transistor density, power efficiency, and clock frequency by distributing critical path gates across different planes.
• Enabling logical folding requires aggressive bonding pitches (sub-two micron hybrid bonding) and fine metal stack ratios, alongside innovations in TSV technology.