Enabling Robust Manufacturing of Photonic Integrated Circuits for the AI Revolution

Full Transcript

https://www.youtube.com/watch?v=oSMUz-hy-LE

[00:10] Thank you very much and welcome welcome.
[00:12] Thank you very much and welcome welcome everyone to the webinar in which we're going to talk about a very important topic in our industry.
[00:17] Today it is all about the robust manufacturing of photonic integrated circuits and how we can do that all together.
[00:28] We have an spectacular spectacular lineup of speakers that are going to rank over all the part important parts of the value chain.
[00:37] Many of you were at OFC this year and we did realize that we have a huge challenge in our industry.
[00:46] Current data centers cannot manage the traffic that AI is going to bring to them in the coming years and for that depend on the physical layer and we know how to do this.
[00:55] We just need to work together.
[00:57] This is the purpose of this webinar.
[00:59] What you're going to witness is how companies can have a piece of the puzzle
[01:01] companies can have a piece of the puzzle and how bringing all together can solve.
[01:04] and how bringing all together can solve this huge challenges of having this.
[01:07] this huge challenges of having this robust manufacturing of reliable.
[01:09] robust manufacturing of reliable integrated photonics in this AI era.
[01:12] integrated photonics in this AI era.
[01:12] Together with me I have companies like.
[01:15] Together with me I have companies like AFL like global foundaries like IBM like.
[01:18] AFL like global foundaries like IBM like I labs quantify photonics.
[01:18] Let's see.
[01:21] I labs quantify photonics.
[01:21] Let's see.
[01:23] Let's understand from them what challenges they have, what solutions.
[01:25] challenges they have, what solutions they have, and how each and one of you.
[01:28] they have, and how each and one of you in the room can help them be successful.
[01:31] in the room can help them be successful and can help the industry integrate.
[01:34] and can help the industry integrate their technology.
[01:34] Today I'm going to.
[01:36] their technology.
[01:36] Today I'm going to have Nick Angra who is the global.
[01:37] have Nick Angra who is the global product lead of AFL who's going to talk.
[01:39] product lead of AFL who's going to talk to us about his work for the advanced.
[01:42] to us about his work for the advanced photonics coalition.
[01:42] Afterwards, Vikas.
[01:44] photonics coalition.
[01:44] Afterwards, Vikas Gupta, the senior director of product.
[01:46] Gupta, the senior director of product management at Global Foundaries is going.
[01:48] management at Global Foundaries is going to talk to us about the advancements in.
[01:50] to talk to us about the advancements in silicon photonics and how those.
[01:53] silicon photonics and how those advancements are matching the demands on.
[01:55] advancements are matching the demands on ultra high bandwidth and reliability.
[01:57] ultra high bandwidth and reliability from the data centers.
[01:57] We'll continue.
[01:59] from the data centers.
[01:59] We'll continue with Alexiski from IBM in Bremont in.
[02:03] with Alexiski from IBM in Bremont in Canada.
[02:06] He's an expert on the packaging and assembly for volume production of complex photonic interative circuits.
[02:10] But when you talk to volume production, you need contact contract manufacturers and the most important the biggest one in the world and in the room today is Jable who will be represented by Joyo Kataniga.
[02:24] You cannot do this if you don't have proper interposers and the best interposers in the world are manufactured by IR labs.
[02:30] Scott Clark will talk to us about this and then afterwards we have everything packaged and with the right interposer on it we are going to test it and for that we have the capabilities of quantify photonics and of course of the giant teradine represented by George urad.
[02:45] Thank you very much all of that all of us for being with us today with no further ado let's get the ball rolling let's get things started.
[02:50] I would like to welcome to the room and to the floor Nick Angra from AFL who today is going to talk to us about the work that he does for the advanced Photonic Coalition.
[03:00] Thank you very much, Nick, for being with us today.
[03:01] The floor and
[03:04] for being with us today.
[03:04] The floor and the attention of a very large audience.
[03:06] the attention of a very large audience.
[03:06] The attention of everyone goes to you.
[03:09] The attention of everyone goes to you.
[03:09] Thank you very much, Jose.
[03:09] Um, I'm just going to bring up my slide deck here in just a second.
[03:13] Thank you for the introduction, guys.
[03:15] Can all see my slides?
[03:17] Okay, you go to presentation mode.
[03:20] Yes, perfectly clear.
[03:22] Okay, excellent.
[03:22] All right.
[03:22] Uh, thanks once again, Jose.
[03:24] Uh, good morning, good afternoon, good evening to everybody.
[03:26] Uh my name is Nick Angra.
[03:28] Um I am uh presenting today as uh the board of director uh for APC and I'm also the working group chair for u uh multicore fiber.
[03:36] Uh that's one of the groups that we have within the APC.
[03:40] Uh my full-time role certainly is with EFL.
[03:42] EFL is is a fiber optic connectivity company.
[03:45] uh today I'll be speaking a little bit to give you guys a bit of a brief on what APC is all about uh and some of the work that which we are doing in the industry.
[03:57] So APC uh stands for advanced photonics coalition and u you know we've uh
[04:05] coalition and you know we've uh basically uh trying to work specifically on on the photonix challenge.
[04:13] Uh this is something I just alluded to just in a few minutes ago.
[04:18] uh there is an increased amount of density and there are solutions that are needed.
[04:22] Uh the challenge with the solutions within the ecosystem is the amount of differentiation right and the other challenge is certainly trying to bring up and uh technology from the grassroot level up uh so that these can be standardized and can be adopted into the industry.
[04:38] So we work across the ecosystem.
[04:41] Uh we work uh in terms of you know uh getting requirements together uh you know down the ecosystem and getting all the technical input on how that could be implemented and really going out in the industry and lowering some of the barriers as far as new technology is concerned.
[04:58] One example is certainly the multi-core fiber working group that I'm chairing right now.
[05:02] And uh we do have u additional uh working groups which I'll
[05:07] additional uh working groups which I'll be talking about in just a second.
[05:10] So u I think very excited to be part of this uh group.
[05:15] Uh we are a growing group uh that has made some very significant um uh advances in the last uh last few months.
[05:24] Uh we have grown every month since we launched.
[05:26] Uh many thanks to Melissa and others in the team.
[05:29] uh this is the group of companies that are part of the advanced photonics coalition.
[05:33] Today uh you see a very significant number of uh names there in terms of who's who's participating in these groups.
[05:44] Uh we are working on uh multiple different uh working groups as well as as we uh as we build our uh standards uh you know ecosystemdriven standards.
[05:56] Here's a snapshot on the executive leadership.
[05:58] Uh the APC is actually led by Jeff Maki.
[06:01] Jeff is out today uh traveling and I'm helping him out on this introduction today.
[06:06] Uh we have Julie Adams who is uh with IBM and the
[06:09] Julie Adams who is uh with IBM and the working group chair for Silicon working group chair for Silicon Photonics.
[06:14] Uh we have Jake Chu from uh DuPont who is a treasurer of the board.
[06:16] DuPont who is a treasurer of the board.
[06:19] Uh Melissa certainly helps us on lots of different areas including uh uh membership and and other activities.
[06:25] membership and and other activities.
[06:28] Joshua uh from Hero. He's our interconnect optical waveguide interconnect system working group chair.
[06:32] interconnect system working group chair.
[06:34] Uh you see my picture there. Uh that's me on the multicore fiber side.
[06:36] And we have Vikas uh who is from uh Global Foundaries who also the board of director uh for uh APC.
[06:41] Foundaries who also the board of director uh for uh APC.
[06:45] And last but not least, we have Brian Hall.
[06:47] Brian helps us host a core package optics working group.
[06:50] Uh he is with Color Ship.
[06:54] So u I think uh I think we've some made some great progress with the with the number of participants we've had uh in the APC.
[06:58] great progress with the with the number of participants we've had uh in the APC.
[07:01] Uh we continuing to work on the photonics challenge in trying to address uh you know what's required by by AI and building up standards.
[07:05] photonics challenge in trying to address uh you know what's required by by AI and building up standards.
[07:07] uh more
[07:11] building up standards.
[07:12] uh more information on the working groups information on the working groups itself.
[07:14] The silicon photonics itself.
[07:17] The silicon photonics manufacturing this is uh lowcost manufacturing right uh this is hosted by Julie Adams uh from IBM uh rack density management all about multi-core fiber uh
[07:23] management all about multi-core fiber uh multi-core fiber basically gives you 4x the amount of density uh that you have in in the current single core compared to current single core.
[07:36] So uh you know you also tend up uh saving about 75% uh uh less materials as well.
[07:43] So this is a multi-core fiber working group.
[07:45] What we're doing here is coming up with solutions, specific solutions that can be used both in the transceivers and CPO
[07:51] and we have a charter that we that's actually getting um some voting right now from the members and we're going to continue to work you know in terms of defining what some of those solutions could be uh in terms of adoption into the industry.
[08:05] The core package optics working group this is hosted by Brian
[08:11] working group this is hosted by Brian Hall.
[08:14] uh he's looking at uh how to solve the challenges and how to have better adoption around core package optics.
[08:19] Core package optics as many of you know has been around for a while.
[08:24] uh we are trying to take a look at it from the point of uh ecosystem driven uh driven by the companies you know reducing differentiation finding more common standards and building this up and certainly Joshua Kum Kim has has been hosting the optical waveguide interconnect system group uh replacing copper uh where he's he's done a significant amount of work over the last year year and a half or or and and more uh in terms of uh you where we see fatonics playing a very important role uh especially in the AI landscape that we are in today.
[09:00] So these are the working groups.
[09:02] I encourage you all to please join us and uh in in these working groups and be part of these standards.
[09:07] It's it's very exciting.
[09:10] um you know you can certainly reach out to me uh or Melissa and we'll be happy to
[09:14] me uh or Melissa and we'll be happy to enroll you guys on and uh you know uh enroll you guys on and uh you know uh grow our uh uh participation as we go.
[09:20] grow our uh uh participation as we go about you know building more and more of these standards.
[09:22] Um that's all I have Jose I will pass it back to you.
[09:25] Thank you very much.
[09:27] Congratulations, Nick, on everything that you and the entire APC coalition is achieving.
[09:34] Bringing these four working groups on the silicon photonics, on the fiber, on the interconnects is something that is bringing all the industry together and that's what it's all about.
[09:45] Thank you for working on that.
[09:47] Thank you very much for also communicating everything that you do on this.
[09:48] Let's now talk to one of the board members of APC.
[09:51] one person who has been thanks to his work advancing global foundaries and silicon photonics together.
[09:58] It is such a huge achievement by this industry having silicon photonics manufacturer global fundaries at this scale with this seriousness.
[10:06] Vikas Gupta thank you very much being with us today.
[10:09] Tell us about the silicon photonist platform and tell us how all of us can help.
[10:13] Let me add one point for
[10:16] of us can help.
[10:16] Let me add one point for everyone this in the room today.
[10:17] We have everyone this in the room today.
[10:17] We have right now 118 participants during the meeting.
[10:22] During the meeting, you can post questions using the Q&A button.
[10:24] Post your questions there to make sure that the speaker today can answer them.
[10:29] In your question, please write your name and company because that gives context to your question.
[10:37] And now with that said, Vikas Gupta, the floor and the attention of everyone is yours.
[10:42] Thank you, Jose.
[10:44] Uh, hi, my name is Vicas Gupta.
[10:45] I lead the product management team for silicon photonix at global foundaries and and today I guess you are going to uh go through a lot of presenters who are going to give their their point of view for that specific industry that they represent.
[10:58] I'm representing the foundry side and so I wanted to give you all a view of things that we are doing from the foundry perspective to enable high volume and robust volume manufacturing for photonix.
[11:10] So let I'm I'm going to start off I'm going to cover sort of three three aspects.
[11:14] The first first thing is
[11:17] three aspects.
[11:17] The first first thing is just uh creating a you know a flexible foundry platform.
[11:23] Uh then I'm going to cover topics associated with wafer level processing and the need for a vibrant ecosystem.
[11:31] So starting off with my first topic uh as a foundry in order to meet the scale for AI based you know photonic interconnects uh there there are multiple options for you know scale out networks which tend to be more standards compliant versus scale up networks which tend to be you know bookended solutions and it is important for a foundry to be able to offer a technology that covers s that design space whether it's co-ackaged optics, pluggable, scale up, scale out and and offer that sort of foundry solution that can be applied across the board for these solutions.
[12:13] And the value to the customer that we bring as we create this
[12:18] customer that we bring as we create this sort of featurerich and flexible.
[12:20] sort of featurerich and flexible technology is the fact that learning.
[12:23] technology is the fact that learning that can the learning can be applied.
[12:25] that can the learning can be applied across these solutions and and it helps.
[12:28] across these solutions and and it helps the customer from a Yale perspective and.
[12:31] the customer from a Yale perspective and for a foundry far foundry provides the.
[12:33] for a foundry far foundry provides the scale and so for global foundaries we.
[12:36] scale and so for global foundaries we have offered GFotonix as our foundry.
[12:39] have offered GFotonix as our foundry platform which is a very rich uh.
[12:42] platform which is a very rich uh platform but it's also extreme extremely.
[12:44] platform but it's also extreme extremely flexible that we can a address all of.
[12:47] flexible that we can a address all of these solutions but depending upon the.
[12:50] these solutions but depending upon the customer system architecture we can.
[12:51] customer system architecture we can offer a monolithic solution or a.
[12:53] offer a monolithic solution or a photonic solution.
[12:56] photonic solution. Monolithic means that we actually integrate you know the RFC.
[12:59] we actually integrate you know the RFC mass along with the photonix and in some.
[13:01] cases where a company may want to do a.
[13:04] cases where a company may want to do a design with a separate EIC we support.
[13:06] design with a separate EIC we support those solutions also and then within the.
[13:10] those solutions also and then within the context of the technology we offer a lot.
[13:12] context of the technology we offer a lot of flexibility to our customers in.
[13:15] of flexibility to our customers in allowing them to do free form designs.
[13:18] allowing them to do free form designs and and the technology actually is able.
[13:20] and and the technology actually is able to comprehend uh these sort of.
[13:23] to comprehend uh these sort of customerdeveloped solutions ions that we can offer as part of the silicon.
[13:27] can offer as part of the silicon solution uh from the foundry side.
[13:30] solution uh from the foundry side. In addition to that, I've already mentioned this, you know, the slow wide or fast and narrow and that that is sort of related to the scale out which tends to be more of fast and narrow and the scale up which will probably be you know proprietary solutions which tend to be slow and wide.
[13:46] proprietary solutions which tend to be slow and wide. So this is all inbuilt into the technology through the device offerings that GF Photonix offers and then you know the need for varied fiber attached solutions in in some cases there's a need for permanently attached fibers some cases there are detachable solutions so it is important for a foundry to be able to comprehend these sort of aspects of a system requirement that the c customer may need.
[14:08] foundry to be able to comprehend these sort of aspects of a system requirement that the c customer may need. So putting all of this together allows the foundry to offer scalable solutions and and also achieve
[14:21] scalable solutions and and also achieve volumes that are required for uh cross.
[14:24] volumes that are required for uh cross cross uh product learning.
[14:27] cross uh product learning.
[14:27] The second aspect in order to meet sort of these scaling requirements is to do everything that we can at wafer level.
[14:31] So one of the trends you will see as even from an OSAD perspective a lot of the advanced processing for packaging that is occurring is occurring more and more at wafer level.
[14:37] whether you start from plating which is you know for bumping requirements TSV TSV reveal wafer sort and that is electrooptical testing.
[14:51] there will be several vendors or and and presenters in this webinar which will talk about wafer scale solutions for electrooptical testing for functional.
[15:01] so as the cost of the packaging becomes higher and higher, you actually want to be able to weed out and and address yield level issues at a wafer level.
[15:10] So more and more work that can be done at a wafer level, the better off you are in terms of reducing the cost but then also
[15:22] terms of reducing the cost but then also scaling up the solution.
[15:25] And we we also want to go to the extreme of you know doing some of parts of the fiber attach if possible at wafer level also.
[15:32] So some of the detachable solutions you can actually start doing turning mirrors and things like that at wafer level.
[15:39] So the more work you can do at wafer level the better scalable the solutions tend to be.
[15:44] And then the last topic that I wanted to cover is you know none of the companies in the ecosystem can do all of this work by themselves.
[15:55] And it is important to establish a vibrant ecosystem that the foundaries can work with but also the customers can work with in terms of finding solutions and that starts from design partners, packaging partners and EDA partners including you know going out to the vendors that are providing lasers that are providing S SOAS, fibers, connectors etc.
[16:19] So part of
[16:23] SOAS, fibers, connectors etc.
[16:26] So part of you know this enablement of solutions for the AI market does require a larger ecosystem as they say.
[16:31] you know it takes a village to raise raise a child but in this case it takes a village to raise these sort of solutions.
[16:38] So I think it's it's an important part for us to have a flexible technologies uh b uh flexible technologies a lot of the wafer level uh uh packaging and testing if possible and then a vibrant ecosystem.
[16:54] So that's that's uh my presentation.
[16:57] Thank you.
[16:59] Thank you very much.
[17:02] Because what would you say are in your opinion the the the biggest challenges that the silicon photonics are facing today coming from this so-called AI revolution?
[17:11] Yeah.
[17:13] So I think in in the past there have been a lot of uh varied solutions that are provided to foundaries which was subscale in terms of raising.
[17:21] I think at at least I would say from our side the
[17:24] at least I would say from our side the fact that we have a flexible platform we.
[17:26] fact that we have a flexible platform we able to minimize solutions that.
[17:29] able to minimize solutions that customers are providing on a technology level.
[17:33] I think there are still solutions that are being provided at a packaging level.
[17:37] and the more that we can standardize some of the packaging options uh I think the better off.
[17:41] everybody will be in the ecosystem to find solutions that are scalable.
[17:48] find solutions that are scalable.
[17:50] I think one of the biggest challenges that we always have with the with the photonix integrated circuits.
[17:54] manufacturing is how to after having the cheap manufacturer how to package it in the right volume for the right cost and.
[18:02] there is where global fundaries you are working as part of this working group together with our next speaker.
[18:05] I would like to welcome Alex Jantaa who is the lead scientist and lead business developer for the packaging and assembly line at IBM Vermont.
[18:15] and we want to hear from them how we can package those silicon photon achieves manufacturer global foundaries reliably and.
[18:25] global foundaries reliably and affordably.
[18:27] Alex, thank you very much affordably.
[18:27] Alex, thank you very much for being with us.
[18:29] The floor and the for being with us.
[18:29] The floor and the attention of everyone goes to IBM.
[18:31] attention of everyone goes to IBM.
[18:33] Thank you Jose for the introduction.
[18:33] So I'm Alexander Jat from IBM.
[18:35] I'm a senior advisory engineering for it integration
[18:37] in photonic packaging and today I will
[18:39] present some of IBM semiconductor work
[18:42] that we're doing on advanced photonic
[18:44] packaging technology for the next
[18:45] generation AI.
[18:47] So sorry if the slides go off smooth.
[18:51] So of course IBM semiconductor is a leading
[18:53] in advanced packaging technology and
[18:55] today I will mostly focus on chiplets
[18:57] and advanced packaging.
[18:59] So what is needed for co- package photonics uh dies
[19:02] close to ASIC dies or generative AI platforms.
[19:05] Of course, IBM has a a full
[19:08] advanced packaging infrastructure from
[19:10] IBM research to IBM Albany as well to
[19:13] the high volume manufacturing from uh uh
[19:16] IBM
[19:21] In fact, IBM Albany has this great
[19:25] In fact, IBM Albany has this great platform for 300 meters.
[19:28] So can they platform for 300 meters.
[19:31] So can they they can support 2.5 3D packaging C4 micro bump bondings RDL advanced bonding.
[19:33] micro bump bondings RDL advanced bonding assembly and thermal characterization.
[19:35] assembly and thermal characterization here some example of products that are assembled at at IBM Pommo.
[19:38] here some example of products that are assembled at at IBM Pommo.
[19:40] So this is the advanced packaging site and as you can see more and more we will see optics coming towards the ASIC uh since there are more power efficiency and also the bandwidth requirements that are required.
[19:43] the advanced packaging site and as you can see more and more we will see optics.
[19:45] coming towards the ASIC uh since there are more power efficiency and also the bandwidth requirements that are required.
[19:47] are more power efficiency and also the bandwidth requirements that are required.
[19:49] bandwidth requirements that are required.
[19:52] required. This is the photonic value proposition.
[19:54] proposition. So of course there's a IO starving and as we can see on the bottom right graph there's a gap between the compute and the interconnect to the uh uh bandwidth or the RAM.
[19:56] So of course there's a IO starving and as we can see on the bottom right graph there's a gap between the.
[19:58] starving and as we can see on the bottom right graph there's a gap between the compute and the interconnect to the uh uh bandwidth or the RAM.
[20:01] right graph there's a gap between the compute and the interconnect to the uh uh bandwidth or the RAM.
[20:04] compute and the interconnect to the uh uh bandwidth or the RAM.
[20:06] uh bandwidth or the RAM. So as you can see we need to close this gap and silicon photonics and co- package optics can answer those support those multi-termit bandwidths with low power and of course be able to scale the AI and machine learning uh required.
[20:08] see we need to close this gap and silicon photonics and co- package optics.
[20:11] silicon photonics and co- package optics can answer those support those multi-termit bandwidths with low power.
[20:13] can answer those support those multi-termit bandwidths with low power and of course be able to scale the AI and machine learning uh required.
[20:16] and of course be able to scale the AI and machine learning uh required.
[20:18] and machine learning uh required.
[20:20] uh required. Here you have a little table.
[20:22] required. Here you have a little table.
[20:24] I won't go through very cruel but you have some composition uh between the
[20:26] have some composition uh between the power the cost the density and the reach
[20:28] power the cost the density and the reach of the LDL interposer fan out packaging
[20:32] of the LDL interposer fan out packaging the memory with HBM3 the various UCI
[20:35] the memory with HBM3 the various UCI standards the PCB the electrical cable
[20:38] standards the PCB the electrical cable then link and electrical socket active
[20:40] then link and electrical socket active octipable cable front plugable obo and
[20:43] octipable cable front plugable obo and you can see how CPO positions uh against
[20:46] you can see how CPO positions uh against those and you can see that the main
[20:48] those and you can see that the main driver is also the power efficiency and
[20:50] driver is also the power efficiency and the density in term of the the bandwidth
[20:53] the density in term of the the bandwidth that can be
[20:55] that can be achieved. Of course, IBM has a full uh
[20:58] achieved. Of course, IBM has a full uh advanced integration. So basically for
[21:00] advanced integration. So basically for all of those little pictograms you have
[21:02] all of those little pictograms you have a department uh regarding uh designing
[21:05] a department uh regarding uh designing package and co- package optics from a
[21:06] package and co- package optics from a switch as to the die and of course
[21:09] switch as to the die and of course packaging is a critical for the success
[21:11] packaging is a critical for the success and all all need have to co-design mine
[21:13] and all all need have to co-design mine and of course we can work with the with
[21:16] and of course we can work with the with their customers to enhance the the
[21:19] their customers to enhance the the target application and
[21:21] target application and needs. Of course I offer a full turnkey
[21:24] needs. Of course I offer a full turnkey solution. So from the electrical pick
[21:26] solution. So from the electrical pick assemblies to the uh optical
[21:28] assemblies to the uh optical interconnect attach the cop test and the
[21:31] interconnect attach the cop test and the uh overall more complex uh system
[21:34] uh overall more complex uh system package to the more complex MCM switches
[21:37] package to the more complex MCM switches or uh AI platform where we can
[21:39] or uh AI platform where we can co-package optics and here have some
[21:41] co-package optics and here have some pictures and example up to the final uh
[21:44] pictures and example up to the final uh optical module
[21:45] optical module test. You have here some uh graphs of of
[21:49] test. You have here some uh graphs of of shamm of integration. So you can see how
[21:50] shamm of integration. So you can see how the fatic die and the electrical die can
[21:53] the fatic die and the electrical die can be co-ackaged and as we see we're going
[21:55] be co-ackaged and as we see we're going to see more and more those 3D packaging
[21:58] to see more and more those 3D packaging as we're going to have an increase in
[21:59] as we're going to have an increase in bandwidth
[22:01] bandwidth speeds. Uh I will let some time to this
[22:04] speeds. Uh I will let some time to this animation. So of course IBM has made
[22:06] animation. So of course IBM has made this press release. Uh so we have this
[22:08] this press release. Uh so we have this amazing uh breakthrough in in kind of
[22:10] amazing uh breakthrough in in kind of bandwidth density of optical
[22:12] bandwidth density of optical interconnect. So as you can see uh I
[22:15] interconnect. So as you can see uh I will show you on next slide
[22:19] uh we have this uh great on optics on
[22:21] uh we have this uh great on optics on package. So we have this uh high density
[22:24] package. So we have this uh high density pitch for optical interconnects uh up to
[22:26] pitch for optical interconnects uh up to 108 channels per connector. Uh and this
[22:30] 108 channels per connector. Uh and this is a a breakthrough. It's like six time
[22:32] is a a breakthrough. It's like six time better than state-of-the-art and we can
[22:34] better than state-of-the-art and we can have a better power reduction as
[22:36] have a better power reduction as well. Of course IBM is also working on
[22:39] well. Of course IBM is also working on the supply chain. So we have all our
[22:41] the supply chain. So we have all our suppliers all over the world and we try
[22:43] suppliers all over the world and we try to have a strong uh supply chain and and
[22:47] to have a strong uh supply chain and and we also have a 100% North American
[22:49] we also have a 100% North American supply chain available if
[22:51] supply chain available if required. I have also to mention that uh
[22:54] required. I have also to mention that uh uh we have some great announcement at
[22:56] uh we have some great announcement at the IBM uh uh bromel so the packaging
[22:58] the IBM uh uh bromel so the packaging site we had some uh help from our
[23:00] site we had some uh help from our governments to help this uh CPU assembly
[23:03] governments to help this uh CPU assembly line. So we have a huge investments and
[23:06] line. So we have a huge investments and we are scaling uh our plans capability
[23:08] we are scaling uh our plans capability mostly to support those generative AI
[23:11] mostly to support those generative AI and uh high performance computing that
[23:13] and uh high performance computing that will use CPU
[23:15] will use CPU assemblies but still one main main gaps
[23:18] assemblies but still one main main gaps is still the test and here you have a
[23:20] is still the test and here you have a little uh overview. Uh so still the test
[23:22] little uh overview. Uh so still the test is still a lot uh uh needs a lot of work
[23:26] is still a lot uh uh needs a lot of work and and collaboration. So of course the
[23:29] and and collaboration. So of course the methodology the model test
[23:30] methodology the model test connectization the standardization of
[23:32] connectization the standardization of that the sub assemblies test as well the
[23:35] that the sub assemblies test as well the electrical optical flow uh the
[23:37] electrical optical flow uh the calibration times the system level tests
[23:40] calibration times the system level tests and the burning and inclusion of MSM's
[23:42] and the burning and inclusion of MSM's SCP because as you know those co package
[23:44] SCP because as you know those co package optics and AI platform will need to have
[23:46] optics and AI platform will need to have very robust and reliable interconnects
[23:49] very robust and reliable interconnects uh to support the workloads. So we
[23:51] uh to support the workloads. So we believe uh burn-in and some uh hall
[23:54] believe uh burn-in and some uh hall validation on the on the CPU package
[23:56] validation on the on the CPU package will be required. Also we need some jet
[23:59] will be required. Also we need some jet uh relability for the CPU as the fatonic
[24:01] uh relability for the CPU as the fatonic die will be close to hot ASIC and we
[24:03] die will be close to hot ASIC and we need to have some fit rate demonstration
[24:05] need to have some fit rate demonstration to be able to scale that and and mostly
[24:08] to be able to scale that and and mostly for those next generation hardware that
[24:10] for those next generation hardware that will be in data center that will be able
[24:12] will be in data center that will be able to uh distribute the memory the compute
[24:15] to uh distribute the memory the compute and have some bandwidth sting steering.
[24:17] and have some bandwidth sting steering. So you can see that there's a a vasical
[24:20] So you can see that there's a a vasical system from the photonix code design,
[24:22] system from the photonix code design, the optimization to the system design,
[24:24] the optimization to the system design, the electrical and everything is driving
[24:26] the electrical and everything is driving through the packaging with all the
[24:28] through the packaging with all the various form factors. So all the optical
[24:30] various form factors. So all the optical interface, the electrical uh interface
[24:32] interface, the electrical uh interface as well need to be more standardized uh
[24:34] as well need to be more standardized uh to be able to to help the the the
[24:37] to be able to to help the the the overall test platform optimization. Uh
[24:40] overall test platform optimization. Uh currently it's too much um how we say
[24:43] currently it's too much um how we say customized for each customer. So we need
[24:44] customized for each customer. So we need a more standardization and we need also
[24:47] a more standardization and we need also to uh acknowledge that this is a co-op
[24:49] to uh acknowledge that this is a co-op optimization effort at the system level.
[24:51] optimization effort at the system level. So all the power efficiency optical
[24:53] So all the power efficiency optical budget and health monitor and redundancy
[24:55] budget and health monitor and redundancy replaceency in the system level needs to
[24:57] replaceency in the system level needs to be taken in account and then at the end
[24:59] be taken in account and then at the end you also need to have the cost
[25:00] you also need to have the cost structure. So so we need have high
[25:02] structure. So so we need have high volume manufacturing adoption. We need
[25:04] volume manufacturing adoption. We need to have some rework repair strategies
[25:06] to have some rework repair strategies and also take a look at the assembly and
[25:08] and also take a look at the assembly and test economics because in co- package
[25:10] test economics because in co- package optics assembly and tests are our main
[25:12] optics assembly and tests are our main driver uh of the overall package
[25:16] driver uh of the overall package cost. You have a little table of our
[25:18] cost. You have a little table of our readiness. So as you see we have a lot
[25:20] readiness. So as you see we have a lot of reliability data and we have great
[25:22] of reliability data and we have great packaging technology to do cache optics.
[25:25] packaging technology to do cache optics. So uh we have the right uh assembly uh
[25:29] So uh we have the right uh assembly uh techniques and and demonstration for
[25:31] techniques and and demonstration for high level reliability.
[25:33] high level reliability. So including corusion packaging is one
[25:35] So including corusion packaging is one key critical success for the next
[25:36] key critical success for the next generation AI. IBM has a great co-acking
[25:39] generation AI. IBM has a great co-acking toolbox. Uh we can help for design for
[25:41] toolbox. Uh we can help for design for effective manufacturing. We have this
[25:43] effective manufacturing. We have this assembly design kit that can help you to
[25:45] assembly design kit that can help you to design your pick and make it compatible
[25:47] design your pick and make it compatible with our assembly ground rules. We have
[25:49] with our assembly ground rules. We have single mode photonic assembly that are
[25:51] single mode photonic assembly that are uh WDM compatible and we basically
[25:53] uh WDM compatible and we basically leverage our micro know and
[25:55] leverage our micro know and infrastructure to achieve high volume
[25:57] infrastructure to achieve high volume manufacturing targets and all our
[25:59] manufacturing targets and all our packaging are compatible with hydroput
[26:02] packaging are compatible with hydroput microity. So if you have any question
[26:04] microity. So if you have any question please don't hesitate to contact me.
[26:06] please don't hesitate to contact me. Thank you very much Alex. Thank you for
[26:08] Thank you very much Alex. Thank you for a great presentation and thank you for
[26:10] a great presentation and thank you for the evolution and miniaturization of
[26:14] the evolution and miniaturization of CPO. What are the biggest challenges
[26:16] CPO. What are the biggest challenges that we have right now? We we we can do
[26:18] that we have right now? We we we can do as you said co- package is not really a
[26:20] as you said co- package is not really a new concept and we've been working on it
[26:21] new concept and we've been working on it for many years but now we have a
[26:23] for many years but now we have a challenge because companies such as
[26:25] challenge because companies such as Nvidia are showing that this is the
[26:28] Nvidia are showing that this is the future for them. What are this
[26:31] future for them. What are this translated into the assembly and
[26:33] translated into the assembly and packaging we need standardizations
[26:35] packaging we need standardizations mostly to support high manufacturing we
[26:37] mostly to support high manufacturing we need more uh more standard electrical
[26:40] need more uh more standard electrical interface and optical interface for
[26:42] interface and optical interface for those co- package optics. So we need to
[26:43] those co- package optics. So we need to have those clearly defined uh in order
[26:45] have those clearly defined uh in order to for the next generation AI and our
[26:47] to for the next generation AI and our hardware infrastructure uh we need to
[26:49] hardware infrastructure uh we need to have this uh this uh basic framework and
[26:52] have this uh this uh basic framework and also to have helped in the test portion
[26:55] also to have helped in the test portion because we believe that the the test is
[26:57] because we believe that the the test is a critical part and having some more
[26:59] a critical part and having some more built-in self tests and self diagnostic
[27:02] built-in self tests and self diagnostic on the CP on the photonic package will
[27:04] on the CP on the photonic package will be very useful.
[27:06] be very useful. What do you want to standardize at the
[27:08] What do you want to standardize at the end of the day? I mean when you talk
[27:09] end of the day? I mean when you talk about a a CPO is this is only a concept
[27:13] about a a CPO is this is only a concept every every company will make their own.
[27:16] every every company will make their own. Are we looking for decision what the
[27:17] Are we looking for decision what the five is five and five it out the the are
[27:20] five is five and five it out the the are we talking about the pitch what would be
[27:22] we talking about the pitch what would be the the the three top things that you
[27:24] the the the three top things that you think APC should standardize on this
[27:26] think APC should standardize on this aspect. So the connectivization impact
[27:29] aspect. So the connectivization impact uh the electrical speeds we see various
[27:31] uh the electrical speeds we see various electrical speeds for example those big
[27:33] electrical speeds for example those big uh switches will need higher speeds than
[27:36] uh switches will need higher speeds than those more efficient data motion uh
[27:39] those more efficient data motion uh devices that will probably run on lower
[27:41] devices that will probably run on lower electrical speeds. So all those
[27:43] electrical speeds. So all those interfaces need to be standardized uh
[27:45] interfaces need to be standardized uh and and and correctly assess regarding
[27:47] and and and correctly assess regarding the pitch regarding the form factor to
[27:50] the pitch regarding the form factor to be able to include. So for photonic
[27:51] be able to include. So for photonic chiplets is a great topics. We see that
[27:53] chiplets is a great topics. We see that UCI is now working on those futonic
[27:55] UCI is now working on those futonic chiplets and try to standardize them. So
[27:57] chiplets and try to standardize them. So that's that's also a good way forward.
[28:01] that's that's also a good way forward. I would like to to now of course keep
[28:03] I would like to to now of course keep encouraging people to to write questions
[28:05] encouraging people to to write questions in the chat. We have actually received
[28:07] in the chat. We have actually received quite many questions. So many of them
[28:10] quite many questions. So many of them actually related to the slides. I I
[28:11] actually related to the slides. I I would like to remind everyone rest
[28:13] would like to remind everyone rest assured if you register for this event
[28:15] assured if you register for this event with the email without typos in your
[28:18] with the email without typos in your mailbox you will receive the slides in
[28:20] mailbox you will receive the slides in the coming hours. But now let's
[28:21] the coming hours. But now let's continue. Thank you very much Alex for a
[28:23] continue. Thank you very much Alex for a great presentation. When you have the
[28:25] great presentation. When you have the cheap package then you want to make sure
[28:27] cheap package then you want to make sure it has the right system engineering to
[28:29] it has the right system engineering to put in systems globally and for that
[28:31] put in systems globally and for that there is a company in our ecosystem that
[28:34] there is a company in our ecosystem that is active in almost all the markets
[28:36] is active in almost all the markets related to semiconductors and talking to
[28:38] related to semiconductors and talking to the giant Jable who today is represented
[28:41] the giant Jable who today is represented in the room by Giorgio Katsanigga
[28:45] in the room by Giorgio Katsanigga product manager and director in Jable
[28:48] product manager and director in Jable Photonics. Thank you very much Giorgio
[28:49] Photonics. Thank you very much Giorgio for being with us. Tell us how you're
[28:51] for being with us. Tell us how you're going to get the chip from IBM in
[28:53] going to get the chip from IBM in Vermont and you're going to make sure it
[28:55] Vermont and you're going to make sure it is scalable and it is in volume
[28:57] is scalable and it is in volume production ASAP because we need it now.
[28:59] production ASAP because we need it now. The floor and the attention of everyone
[29:01] The floor and the attention of everyone goes to Georgia, goes to Jable.
[29:04] goes to Georgia, goes to Jable. Thank you. Thank you, Jose. I will try
[29:07] Thank you. Thank you, Jose. I will try to answer your question. Of course, it's
[29:09] to answer your question. Of course, it's not so easy straightforward, but I will
[29:11] not so easy straightforward, but I will try for sure. Yeah. So, my name is
[29:13] try for sure. Yeah. So, my name is George Kataniga. I work as a PLM lead
[29:18] George Kataniga. I work as a PLM lead director in JB Photonics. uh meaning
[29:21] director in JB Photonics. uh meaning let's say product manager for products
[29:23] let's say product manager for products but as well capabilities and today we
[29:25] but as well capabilities and today we are speaking about capabilities
[29:27] are speaking about capabilities uh the the first slide I would like to
[29:30] uh the the first slide I would like to to comment first is okay taking as
[29:33] to comment first is okay taking as example the CPO that for sure in AI is
[29:36] example the CPO that for sure in AI is becoming important application of peak
[29:40] becoming important application of peak and silicon photonics which are the
[29:42] and silicon photonics which are the targets and uh let's say what are the
[29:46] targets and uh let's say what are the impact in term of manufacturing and
[29:48] impact in term of manufacturing and where manufacturing can help. So I
[29:50] where manufacturing can help. So I distinguish in this table let's say some
[29:52] distinguish in this table let's say some of the parameter getting some of the
[29:54] of the parameter getting some of the numbers coming from OC. Obviously was a
[29:57] numbers coming from OC. Obviously was a great show. There were a lot of
[29:58] great show. There were a lot of presentation but also a lot of
[30:00] presentation but also a lot of information shared. For example for what
[30:02] information shared. For example for what is concerning AI and CPO distinguishing
[30:05] is concerning AI and CPO distinguishing between the uh scale out and scale up
[30:07] between the uh scale out and scale up application. uh we see power consumption
[30:10] application. uh we see power consumption as one of the first goal where the scale
[30:12] as one of the first goal where the scale out likely could have a five sixp job
[30:14] out likely could have a five sixp job per bit target while for the scale up is
[30:17] per bit target while for the scale up is much more aggressive going one 1.5 bit
[30:20] much more aggressive going one 1.5 bit job per bit but also in term of cost per
[30:23] job per bit but also in term of cost per bit the the scale up at least the
[30:25] bit the the scale up at least the targets would be very very challenging
[30:27] targets would be very very challenging so one cent per gigabit compared with
[30:30] so one cent per gigabit compared with maybe 10 cent or 20 that could be the
[30:33] maybe 10 cent or 20 that could be the scale out target and uh the target here
[30:36] scale out target and uh the target here is to have a solution in the market
[30:38] is to have a solution in the market quickly. So means that one of the
[30:40] quickly. So means that one of the targets is to decrease the time from the
[30:43] targets is to decrease the time from the design to the mass production. So really
[30:45] design to the mass production. So really to go from years to months. So when we
[30:49] to go from years to months. So when we speak about manufacturing in particular
[30:50] speak about manufacturing in particular the the second and the third aspect. So
[30:52] the the second and the third aspect. So the let's say the the cost and the
[30:56] the let's say the the cost and the overall cost per bit and the time to
[30:58] overall cost per bit and the time to market are important aspect we we are
[31:00] market are important aspect we we are considering we have to
[31:01] considering we have to consider. Let's also
[31:05] consider. Let's also uh let's say get a common let's say
[31:07] uh let's say get a common let's say background or common understanding of
[31:09] background or common understanding of what we mean for example for a CPU
[31:10] what we mean for example for a CPU solution which are the building blocks.
[31:12] solution which are the building blocks. So the first one is for sure the
[31:14] So the first one is for sure the interface the electric interface as I
[31:16] interface the electric interface as I just mentioned today there are some
[31:18] just mentioned today there are some standard like UCI that is becoming
[31:21] standard like UCI that is becoming standard for chiplets but also for peak
[31:23] standard for chiplets but also for peak when connected to let's say in a CPU
[31:26] when connected to let's say in a CPU application to an electronic chip but
[31:29] application to an electronic chip but also uh other application require maybe
[31:32] also uh other application require maybe different standard different rates and
[31:34] different standard different rates and so this for sure is one of the topic
[31:36] so this for sure is one of the topic because different rates means different
[31:38] because different rates means different maybe packaging requirement. The second
[31:40] maybe packaging requirement. The second one let's say not less important is the
[31:42] one let's say not less important is the the fiber touch that is important point
[31:46] the fiber touch that is important point to um to define but as well to in term
[31:50] to um to define but as well to in term of manufacturing to perform today there
[31:53] of manufacturing to perform today there are detachable unit there are fiber unit
[31:56] are detachable unit there are fiber unit not detachable so different let's say uh
[31:59] not detachable so different let's say uh activities different processes defined
[32:01] activities different processes defined for the uh different technology in
[32:04] for the uh different technology in different solution the third aspect is
[32:07] different solution the third aspect is the laser there can be solution with
[32:09] the laser there can be solution with internal Internal laser, external laser.
[32:10] internal Internal laser, external laser. In case of external laser becomes
[32:13] In case of external laser becomes another building blocks in the uh
[32:15] another building blocks in the uh subsystem that can be a PCB, can be a
[32:19] subsystem that can be a PCB, can be a board. In case of internal laser becomes
[32:21] board. In case of internal laser becomes instead something that should be
[32:23] instead something that should be attached at the vafia level or the chip
[32:24] attached at the vafia level or the chip level. So becomes again an issue on
[32:27] level. So becomes again an issue on photonix packaging and and finally is
[32:30] photonix packaging and and finally is the attachment between the electronic
[32:32] the attachment between the electronic and the photonics. So as mentioned also
[32:34] and the photonics. So as mentioned also in in previous contribution how to
[32:36] in in previous contribution how to attach a for example a silicon photonics
[32:39] attach a for example a silicon photonics pick through let's say um with a linear
[32:44] pick through let's say um with a linear driver or with TIA using let's say
[32:46] driver or with TIA using let's say different bumping architecture different
[32:49] different bumping architecture different 2.5D or 3D architecture and eventually
[32:52] 2.5D or 3D architecture and eventually also converting and having also some
[32:54] also converting and having also some electronic chip that convert the rate uh
[32:57] electronic chip that convert the rate uh that is used externally so for example
[32:59] that is used externally so for example the UCI to the internal rate so all this
[33:02] the UCI to the internal rate so all this stuff again are manufacturing related
[33:04] stuff again are manufacturing related each of these element represent a
[33:07] each of these element represent a cost. So uh first of all what we are
[33:10] cost. So uh first of all what we are doing as JBL and then we will go through
[33:12] doing as JBL and then we will go through some some points related how to ensure
[33:16] some some points related how to ensure manufacturing to be really robust that
[33:18] manufacturing to be really robust that is the one of the topic of today. So if
[33:21] is the one of the topic of today. So if we look to the let's say the global
[33:23] we look to the let's say the global let's say life cycle of design uh we are
[33:26] let's say life cycle of design uh we are not doing as J design and of course
[33:28] not doing as J design and of course there are many company doing different
[33:30] there are many company doing different design we are not doing we are not a
[33:32] design we are not doing we are not a foundry so uh we receive a foundry we
[33:36] foundry so uh we receive a foundry we receive let's say buffer from foundry
[33:38] receive let's say buffer from foundry sorry with this pointer is a bit
[33:40] sorry with this pointer is a bit difficult but anyway and what we do in J
[33:42] difficult but anyway and what we do in J is mostly to start at the buffer level
[33:45] is mostly to start at the buffer level including buffer level processing
[33:48] including buffer level processing including let's say dicing grind finding
[33:51] including let's say dicing grind finding and as well testing. And then once the
[33:53] and as well testing. And then once the chip is diced, what we do is that we use
[33:56] chip is diced, what we do is that we use this chip in the context of the
[33:59] this chip in the context of the application including activities like
[34:01] application including activities like flip chip like attachment of fiber or
[34:03] flip chip like attachment of fiber or lens and fiber attaching lid if it is
[34:07] lens and fiber attaching lid if it is the application and testing and then
[34:09] the application and testing and then delivering to the subsystem level that
[34:13] delivering to the subsystem level that can be a board can be a blade inside the
[34:15] can be a board can be a blade inside the system can be a module can be a
[34:17] system can be a module can be a transceiver PCB and finally delivering
[34:20] transceiver PCB and finally delivering the full let's say system with
[34:21] the full let's say system with integration ated in this example in this
[34:24] integration ated in this example in this case CPO. So these are let's say where
[34:26] case CPO. So these are let's say where JB can contribute and and can be let's
[34:28] JB can contribute and and can be let's say also complementaryary to the the
[34:30] say also complementaryary to the the other companies but if we now look to to
[34:35] other companies but if we now look to to be robust uh what we have to look in
[34:38] be robust uh what we have to look in particular for what is concerning cost
[34:40] particular for what is concerning cost are different factors and I'm not
[34:42] are different factors and I'm not looking here to the bomb cost the bomb
[34:44] looking here to the bomb cost the bomb cost depends from the vafers or from the
[34:46] cost depends from the vafers or from the foundry from the fabrication from the
[34:48] foundry from the fabrication from the real material what I'm looking here is
[34:50] real material what I'm looking here is more to the manufacturing cost in
[34:53] more to the manufacturing cost in particular to the items to the the
[34:55] particular to the items to the the parameter that are typically uh the
[34:57] parameter that are typically uh the impacting the cost that are the yield
[35:00] impacting the cost that are the yield and the yield depends a lot from the
[35:02] and the yield depends a lot from the process. So a good process definition
[35:05] process. So a good process definition can bring to high yield from the
[35:07] can bring to high yield from the beginning. A bad process can start
[35:10] beginning. A bad process can start really with very very let's say uh low
[35:12] really with very very let's say uh low yield. Uh consider simply that with 50%
[35:16] yield. Uh consider simply that with 50% yield the cost becomes double. So means
[35:19] yield the cost becomes double. So means that you are paying two times if the
[35:21] that you are paying two times if the yield is very bad. The target is always
[35:23] yield is very bad. The target is always to be let's say 90% higher. So means to
[35:26] to be let's say 90% higher. So means to try to reach the let's say 95% or more.
[35:29] try to reach the let's say 95% or more. But of course at the beginning could be
[35:30] But of course at the beginning could be really an issue and in particular if the
[35:33] really an issue and in particular if the process has not been defined. The second
[35:35] process has not been defined. The second point and is also about yield is to
[35:38] point and is also about yield is to choose the right process option. For
[35:40] choose the right process option. For example, one of the topic we always uh
[35:44] example, one of the topic we always uh touch is the epoxy selection. That is
[35:46] touch is the epoxy selection. That is critical for yield and also reliability
[35:48] critical for yield and also reliability because once you define a certain
[35:50] because once you define a certain receipt for let's say a product how to
[35:53] receipt for let's say a product how to attach fiber or how to attach together
[35:55] attach fiber or how to attach together the different components then you need
[35:57] the different components then you need to uh to be reliable and so this can be
[35:59] to uh to be reliable and so this can be an issue for crit critical let's say for
[36:01] an issue for crit critical let's say for yield but also for reliability.
[36:04] yield but also for reliability. Second parameter is the efficiency in
[36:06] Second parameter is the efficiency in term of unit per hour. Again reducing
[36:09] term of unit per hour. Again reducing the cost means increase the throughput.
[36:12] the cost means increase the throughput. So means the unit per hour and in this
[36:14] So means the unit per hour and in this is important what we provide as
[36:16] is important what we provide as contribution in term of automation.
[36:18] contribution in term of automation. Automation is an important step in order
[36:21] Automation is an important step in order to uh avoid of course touch points and
[36:23] to uh avoid of course touch points and means reduce the unitary cost but as
[36:26] means reduce the unitary cost but as well test and test as mentioned it as
[36:30] well test and test as mentioned it as well as a key point because at the end
[36:32] well as a key point because at the end is a trade-off. You need to be reliable.
[36:35] is a trade-off. You need to be reliable. You need to have a high quality. But on
[36:37] You need to have a high quality. But on the other end, you are not to uh forget
[36:40] the other end, you are not to uh forget that you cannot impact too much the unit
[36:42] that you cannot impact too much the unit per hour. And and finally the investment
[36:45] per hour. And and finally the investment in term of capex in sense that each
[36:47] in term of capex in sense that each investment to produce is let's say
[36:50] investment to produce is let's say impacting the cost and to minimize that
[36:53] impacting the cost and to minimize that is important to have as also mentioned a
[36:55] is important to have as also mentioned a standardized process to avoid to have a
[36:58] standardized process to avoid to have a specific capex means machine for
[37:00] specific capex means machine for specific projects but as well to have at
[37:03] specific projects but as well to have at the end I volume because the the capex
[37:06] the end I volume because the the capex is minimized if you want is absorbed as
[37:08] is minimized if you want is absorbed as much as the volume is high. So these if
[37:10] much as the volume is high. So these if you want are let's say three parameters
[37:12] you want are let's say three parameters that we consider important to get the
[37:14] that we consider important to get the cost down and so to reduce let's say the
[37:17] cost down and so to reduce let's say the the final price in the market for the
[37:20] the final price in the market for the application but uh trying to answer
[37:22] application but uh trying to answer instead the question about the volume
[37:24] instead the question about the volume scale manufacturing to be robust. What
[37:27] scale manufacturing to be robust. What we see as well is that there are choice
[37:29] we see as well is that there are choice that are taken in advance in the life
[37:31] that are taken in advance in the life cycle of the product that can impact
[37:34] cycle of the product that can impact later the fact that the design is robust
[37:36] later the fact that the design is robust enough to be manufactured at the right
[37:38] enough to be manufactured at the right cost.
[37:39] cost. For example, at design level using
[37:42] For example, at design level using standard building blocks maybe
[37:46] standard building blocks maybe again maybe having some trade-off with
[37:49] again maybe having some trade-off with performance is sometimes better than
[37:51] performance is sometimes better than having the best performance but having a
[37:53] having the best performance but having a products with difficulty to be
[37:55] products with difficulty to be manufactured. H try to use existing
[37:58] manufactured. H try to use existing solution for the most complex issue. For
[38:01] solution for the most complex issue. For example, the fiber attachment and the
[38:02] example, the fiber attachment and the metal plating are for sure two critical
[38:05] metal plating are for sure two critical aspects. If you define a very specific
[38:07] aspects. If you define a very specific process for that you can maybe either
[38:09] process for that you can maybe either have a longer cost or sorry a longer
[38:11] have a longer cost or sorry a longer time lead time or a higher cost and uh
[38:15] time lead time or a higher cost and uh for this is important at the design
[38:17] for this is important at the design level or also to think about the
[38:20] level or also to think about the trade-off between performance and
[38:21] trade-off between performance and manufacturability.
[38:23] manufacturability. In the second phase typically after
[38:25] In the second phase typically after design that we can call MPI. Uh one
[38:28] design that we can call MPI. Uh one important point is to define the same
[38:29] important point is to define the same receipt at this level respect to the one
[38:32] receipt at this level respect to the one that will be used in the large scale
[38:34] that will be used in the large scale manufacturing and as JB we think this
[38:36] manufacturing and as JB we think this very fundamental for this reason we have
[38:38] very fundamental for this reason we have open in in Ottawa an MPI center for
[38:42] open in in Ottawa an MPI center for photonix packaging where we replicate in
[38:44] photonix packaging where we replicate in a small volume what we can do then in
[38:47] a small volume what we can do then in the large scale manufacturing sites. The
[38:49] the large scale manufacturing sites. The other point is to perform what is called
[38:51] other point is to perform what is called design for manu manufacturability and
[38:54] design for manu manufacturability and design for testing. This phase done an
[38:56] design for testing. This phase done an NPI phase allows you to solve the issue
[38:59] NPI phase allows you to solve the issue that can be later big issues and then
[39:02] that can be later big issues and then that is a bit connected with the first
[39:04] that is a bit connected with the first one use the same machine for the large
[39:05] one use the same machine for the large scale
[39:07] scale manufacturing. Finally uh the aspects
[39:10] manufacturing. Finally uh the aspects that are strictly related to the
[39:12] that are strictly related to the manufacturing. So when you arrive to the
[39:14] manufacturing. So when you arrive to the manufacturing phase is really to let's
[39:17] manufacturing phase is really to let's say improve the yield. So to have let's
[39:20] say improve the yield. So to have let's so the capability to increase via via
[39:22] so the capability to increase via via the yield and automatize in order to
[39:24] the yield and automatize in order to decrease the the overall
[39:29] cost. Thank you. Thank you for thank you
[39:33] cost. Thank you. Thank you for thank you very much Georgio. We actually have
[39:34] very much Georgio. We actually have questions in the chat but the first one
[39:37] questions in the chat but the first one I I think is actually for me so I'm
[39:39] I I think is actually for me so I'm going to answer it. Who are the standard
[39:40] going to answer it. Who are the standard vendors for the UCL platform? I mean,
[39:43] vendors for the UCL platform? I mean, let let me know that you're talking
[39:45] let let me know that you're talking about the the chiplets. H the standard
[39:48] about the the chiplets. H the standard vendors we all know them. They are
[39:49] vendors we all know them. They are Nvidia, Marvel, Torrent, Intel, AMD. But
[39:52] Nvidia, Marvel, Torrent, Intel, AMD. But if you are talking about an optical an
[39:55] if you are talking about an optical an optical
[39:56] optical chiplet actually the only one the
[39:59] chiplet actually the only one the world's first UCLA is from Labs. It's
[40:03] world's first UCLA is from Labs. It's the world's first and they are going to
[40:05] the world's first and they are going to present it later in the next
[40:06] present it later in the next presentation. But before we do that,
[40:09] presentation. But before we do that, Giorgio, we have a couple of questions
[40:10] Giorgio, we have a couple of questions for you. The first one is actually quite
[40:12] for you. The first one is actually quite difficult for you to answer because
[40:14] difficult for you to answer because there are many. Where is Jable's CPO
[40:17] there are many. Where is Jable's CPO assembly site?
[40:19] assembly site? Yeah, so uh today we have the MPI site
[40:21] Yeah, so uh today we have the MPI site in Ottawa where we do let's say the
[40:24] in Ottawa where we do let's say the again the process definition and the
[40:27] again the process definition and the large scale manufacturing is in Malaysia
[40:29] large scale manufacturing is in Malaysia in Penanga where we have the photonics
[40:32] in Penanga where we have the photonics if you want site.
[40:34] if you want site. The second question could be for you but
[40:36] The second question could be for you but also for Alexanta. The question is what
[40:39] also for Alexanta. The question is what is the preferred fiber array platform
[40:41] is the preferred fiber array platform polymer plastic silicon V groups? The
[40:44] polymer plastic silicon V groups? The form factor and cost is sensitive. Is
[40:46] form factor and cost is sensitive. Is silicon V group attractive as cost
[40:49] silicon V group attractive as cost effective
[40:51] effective option. Yeah. So it's not easy to give a
[40:54] option. Yeah. So it's not easy to give a let's say black and white solution
[40:56] let's say black and white solution because again this is an example where
[40:58] because again this is an example where we can have a different solution solving
[41:00] we can have a different solution solving some issues but maybe creating other
[41:02] some issues but maybe creating other issue. So it's not easy to compare here
[41:06] issue. So it's not easy to compare here but for sure what needs to be done is a
[41:09] but for sure what needs to be done is a comparison not only at the performance
[41:10] comparison not only at the performance level but also at the manufacturing
[41:13] level but also at the manufacturing level means let's say the the time
[41:16] level means let's say the the time needed to manufacture photonics what is
[41:18] needed to manufacture photonics what is needed in ter machine the accuracy so
[41:21] needed in ter machine the accuracy so what you need to to do and then the
[41:22] what you need to to do and then the final that you can achieve
[41:25] final that you can achieve maybe I can add add to the comments go
[41:28] maybe I can add add to the comments go ahead so silicon V group has the
[41:30] ahead so silicon V group has the advantage to shift the packaging
[41:31] advantage to shift the packaging complexity to the wafer and you can have
[41:33] complexity to the wafer and you can have self alignment and extremely high
[41:35] self alignment and extremely high throughput uh assembly techniques. Uh so
[41:38] throughput uh assembly techniques. Uh so this is very appealing and then based on
[41:40] this is very appealing and then based on your application needs and density then
[41:42] your application needs and density then you can have some polymer waveguides
[41:44] you can have some polymer waveguides that have like 51 optical part per
[41:46] that have like 51 optical part per millimeter bandwidth capacity and
[41:48] millimeter bandwidth capacity and they're still high volume manufacturer
[41:49] they're still high volume manufacturer manufacturing compatible. Uh so
[41:52] manufacturing compatible. Uh so basically we have to look at your
[41:53] basically we have to look at your application what is your foundry
[41:56] application what is your foundry section. uh GF has a great V-groove
[41:58] section. uh GF has a great V-groove platform uh where we can package optical
[42:01] platform uh where we can package optical fiber quite efficiently. So we have uh
[42:05] fiber quite efficiently. So we have uh the right packaging solution. It's it's
[42:06] the right packaging solution. It's it's a matter of your application and and
[42:08] a matter of your application and and this will steer you toward the right uh
[42:10] this will steer you toward the right uh optical interconnect technology.
[42:12] optical interconnect technology. Thank you very much Alex. So silicon V
[42:15] Thank you very much Alex. So silicon V groupoups are attractive as cost
[42:17] groupoups are attractive as cost effective options. The final question
[42:20] effective options. The final question again for you Giorgio is what are your
[42:22] again for you Giorgio is what are your thoughts on the touchable fiber
[42:24] thoughts on the touchable fiber regarding fiber arrays.
[42:27] regarding fiber arrays. Yeah.
[42:28] Yeah. So when you go let's say out from the
[42:32] So when you go let's say out from the single pick itself but you go at the
[42:34] single pick itself but you go at the system level for sure the touchable
[42:36] system level for sure the touchable optics has a big advantages. Why?
[42:38] optics has a big advantages. Why? Because if you want to have and to uh
[42:41] Because if you want to have and to uh use your SMT line that you use for the
[42:44] use your SMT line that you use for the typical electronic mounting also for the
[42:46] typical electronic mounting also for the pick is very difficult to do this if
[42:49] pick is very difficult to do this if they are fiber attached. So instead if
[42:51] they are fiber attached. So instead if you attach let's say what we can call
[42:53] you attach let's say what we can call the socket and then you use a detachable
[42:55] the socket and then you use a detachable optics is much more easy. So this for
[42:58] optics is much more easy. So this for sure is an advantage from the overall
[43:00] sure is an advantage from the overall process to for the CPU in particular to
[43:03] process to for the CPU in particular to mount a large quantity of fiber around
[43:05] mount a large quantity of fiber around the Ethernet switch or whatever it is. I
[43:08] the Ethernet switch or whatever it is. I am extremely optimistic that we're going
[43:10] am extremely optimistic that we're going to have pluggable fiber arrays for CPO.
[43:13] to have pluggable fiber arrays for CPO. I think actually I believe there is no
[43:14] I think actually I believe there is no other way. H but thank you very much
[43:17] other way. H but thank you very much Giorgio. Congratulations you're
[43:19] Giorgio. Congratulations you're achieving and congratulations to the
[43:20] achieving and congratulations to the next speaker. I think this one is for me
[43:23] next speaker. I think this one is for me my favorite presentation today. A month
[43:25] my favorite presentation today. A month ago a company in United States Ayar Labs
[43:29] ago a company in United States Ayar Labs shock the world with an announcement 8
[43:30] shock the world with an announcement 8 teraby per second bandwidth on an
[43:32] teraby per second bandwidth on an optical chiplet. Since that
[43:34] optical chiplet. Since that announcement, everybody has been
[43:36] announcement, everybody has been wondering how they do it. And today, I'm
[43:38] wondering how they do it. And today, I'm not gonna say they're gonna tell us how
[43:40] not gonna say they're gonna tell us how they do it, but they're gonna tell us
[43:41] they do it, but they're gonna tell us what they do. Scott Clark, thank you.
[43:43] what they do. Scott Clark, thank you. First of all, congratulations on
[43:44] First of all, congratulations on everything that I love is achieving. And
[43:46] everything that I love is achieving. And thank you very much for being with us
[43:48] thank you very much for being with us today. The floor and the attention of
[43:50] today. The floor and the attention of everyone goes to you. Well, thank you,
[43:53] everyone goes to you. Well, thank you, Jose. Uh that was a a terrific segue.
[43:56] Jose. Uh that was a a terrific segue. Um, as you mentioned at OFC, uh, IR
[43:59] Um, as you mentioned at OFC, uh, IR Labs, we did demonstrate, uh, the
[44:01] Labs, we did demonstrate, uh, the world's first, uh, optically enabled UCI
[44:04] world's first, uh, optically enabled UCI chiplet, uh, closing a full, uh, link at
[44:07] chiplet, uh, closing a full, uh, link at 8 terabits per second. And IR Labs,
[44:09] 8 terabits per second. And IR Labs, we're a fab semiconductor chiplet
[44:13] we're a fab semiconductor chiplet company. Uh but we not only do um EIC
[44:16] company. Uh but we not only do um EIC PIC monolithic uh chiplet, we also have
[44:18] PIC monolithic uh chiplet, we also have our own uh laser light source solution
[44:21] our own uh laser light source solution that together uh we call um an optical
[44:24] that together uh we call um an optical IO solution uh for integration. Um we've
[44:28] IO solution uh for integration. Um we've been at this for a number of years. Uh
[44:29] been at this for a number of years. Uh Labs as a company uh is celebrating our
[44:32] Labs as a company uh is celebrating our 10th anniversary this month. Uh but
[44:34] 10th anniversary this month. Uh but we're still very much a fast-paced
[44:36] we're still very much a fast-paced startup company uh in in just an
[44:38] startup company uh in in just an exciting space right now.
[44:41] exciting space right now. um to really uh address uh the question
[44:44] um to really uh address uh the question or the topic at hand. Um really uh as a
[44:47] or the topic at hand. Um really uh as a fabulous semiconductor company um we see
[44:50] fabulous semiconductor company um we see that getting to a known good die is the
[44:53] that getting to a known good die is the critical enabler to getting to robust
[44:55] critical enabler to getting to robust high volume. Um there's a few challenges
[44:59] high volume. Um there's a few challenges in this. Um but first you know uh just
[45:03] in this. Um but first you know uh just in the last 18 to 24 months uh a lot of
[45:06] in the last 18 to 24 months uh a lot of things have shifted. What we've seen is
[45:08] things have shifted. What we've seen is um a shift from questioning uh the
[45:10] um a shift from questioning uh the viability of the technology to more of
[45:12] viability of the technology to more of an acceptance and now there's more um
[45:15] an acceptance and now there's more um discussion and topics around solutions
[45:17] discussion and topics around solutions and implementation and scaling of these
[45:19] and implementation and scaling of these technologies across the board for the
[45:21] technologies across the board for the entire ecosystem. So within that uh the
[45:25] entire ecosystem. So within that uh the industry we're we're in a deep into the
[45:27] industry we're we're in a deep into the learning curves in multiple areas. um as
[45:30] learning curves in multiple areas. um as some some of the uh presenters have have
[45:33] some some of the uh presenters have have uh raised uh there is just the inherent
[45:35] uh raised uh there is just the inherent silicon design right and uh figuring out
[45:38] silicon design right and uh figuring out uh some of the design approaches uh
[45:41] uh some of the design approaches uh there's the foundry PDK and the foundry
[45:43] there's the foundry PDK and the foundry process and the maturity um that that
[45:46] process and the maturity um that that goes through um there is a chemical and
[45:49] goes through um there is a chemical and material science as well that not only
[45:52] material science as well that not only goes into uh the wafer processing but
[45:54] goes into uh the wafer processing but then everything uh into the packaging
[45:57] then everything uh into the packaging the substrates uh etc. etc. to make
[46:00] the substrates uh etc. etc. to make these solutions work. And then finally
[46:03] these solutions work. And then finally um a large area that still needs to be
[46:05] um a large area that still needs to be addressed and is being addressed um is
[46:07] addressed and is being addressed um is in the area of test uh not just at wafer
[46:11] in the area of test uh not just at wafer and die but also at package and system
[46:13] and die but also at package and system level as well. So all of these are um
[46:16] level as well. So all of these are um these industry players are are jumping
[46:18] these industry players are are jumping in and addressing these. We're very
[46:20] in and addressing these. We're very rapidly going through this maturity uh
[46:22] rapidly going through this maturity uh learning curve. Um and it's exciting.
[46:26] learning curve. Um and it's exciting. It's exciting to see because it's coming
[46:28] It's exciting to see because it's coming together very very
[46:29] together very very rapidly. So all of these elements uh do
[46:32] rapidly. So all of these elements uh do contribute to higher yields and and
[46:35] contribute to higher yields and and getting to tested qualified uh known
[46:37] getting to tested qualified uh known good die uh that allows for robust
[46:40] good die uh that allows for robust volume
[46:41] volume manufacturing. Um and again as I said
[46:44] manufacturing. Um and again as I said we've seen significant process I'm sorry
[46:46] we've seen significant process I'm sorry uh progress in all of these fronts in
[46:49] uh progress in all of these fronts in just the last 12 to 18 months. and Labs
[46:53] just the last 12 to 18 months. and Labs is working with many of the panel
[46:55] is working with many of the panel speakers companies um here
[46:58] speakers companies um here today. So we can't really uh ignore what
[47:03] today. So we can't really uh ignore what happens after we get um past silicon. Uh
[47:06] happens after we get um past silicon. Uh so once we get to KGD there's another
[47:08] so once we get to KGD there's another challenge uh that um a lot of the
[47:11] challenge uh that um a lot of the speakers have kind of um uh raised and
[47:14] speakers have kind of um uh raised and that's more associated with the back end
[47:16] that's more associated with the back end and bringing this entire solution
[47:18] and bringing this entire solution together. Um so there are challenges
[47:21] together. Um so there are challenges that are being addressed um as people
[47:24] that are being addressed um as people like Alex and and um Giorgio have have
[47:27] like Alex and and um Giorgio have have pointed out in advanced packaging
[47:30] pointed out in advanced packaging uh uh laser light sources. Uh Labs today
[47:34] uh uh laser light sources. Uh Labs today has uh their own 16 lambda uh laser
[47:38] has uh their own 16 lambda uh laser light source that works with our optical
[47:40] light source that works with our optical chiplet. uh but we do see uh large laser
[47:43] chiplet. uh but we do see uh large laser companies now starting to step into this
[47:45] companies now starting to step into this realm of high density uh laser light
[47:48] realm of high density uh laser light sources to support these um optical uh
[47:51] sources to support these um optical uh technologies. Uh as was just addressed
[47:54] technologies. Uh as was just addressed by Giorgio um and Alex alike uh we're
[47:57] by Giorgio um and Alex alike uh we're now getting into fiber attach solutions
[47:59] now getting into fiber attach solutions whether it be uh say Vgroove based uh
[48:02] whether it be uh say Vgroove based uh direct fiber attach um and now
[48:04] direct fiber attach um and now detachable connector solutions as well.
[48:07] detachable connector solutions as well. So we're starting to see those solutions
[48:08] So we're starting to see those solutions come to the forefront. Uh and it's very
[48:11] come to the forefront. Uh and it's very much needed to to make the um the uh
[48:14] much needed to to make the um the uh solution work within a manufacturing
[48:17] solution work within a manufacturing uh realm as well as uh for field
[48:19] uh realm as well as uh for field serviceability. Um and those detachable
[48:22] serviceability. Um and those detachable connectors are coming in both grading
[48:23] connectors are coming in both grading coupler and edge um edge coupled
[48:25] coupler and edge um edge coupled solutions as well. And then finally um
[48:29] solutions as well. And then finally um again once you integrate this silicon
[48:31] again once you integrate this silicon and you're at the MCP level uh managing
[48:35] and you're at the MCP level uh managing that optically enabled MCP through a
[48:38] that optically enabled MCP through a board manufacturing flow as well as well
[48:40] board manufacturing flow as well as well as a board build and system level um
[48:43] as a board build and system level um flow. This is where uh more and more
[48:46] flow. This is where uh more and more electrol optical test solutions are
[48:48] electrol optical test solutions are required. Um and so we truly need a
[48:52] required. Um and so we truly need a robust uh high volume enabled backend
[48:56] robust uh high volume enabled backend ecosystem to enable the front end um of
[49:00] ecosystem to enable the front end um of of
[49:03] silicon. So um as I mentioned before uh
[49:07] silicon. So um as I mentioned before uh we are collaborating uh with a lot of
[49:10] we are collaborating uh with a lot of the companies that are on this uh panel
[49:12] the companies that are on this uh panel and these are some of our partners. Uh
[49:14] and these are some of our partners. Uh we've partnered with uh foundaries um
[49:18] we've partnered with uh foundaries um OSATs uh detachable connector companies
[49:21] OSATs uh detachable connector companies uh we have a lot of uh different uh
[49:23] uh we have a lot of uh different uh development and uh strategic uh
[49:26] development and uh strategic uh engagements and uh we are we are um
[49:30] engagements and uh we are we are um we're championing um this collaboration
[49:33] we're championing um this collaboration industry collaboration across the OSAT
[49:35] industry collaboration across the OSAT and and EMS partners to enable this high
[49:38] and and EMS partners to enable this high volume robust um
[49:40] volume robust um ecosystem. And then finally uh Jose as
[49:43] ecosystem. And then finally uh Jose as you as you mentioned uh yes at OFC we we
[49:46] you as you mentioned uh yes at OFC we we did demonstrate the first optically
[49:47] did demonstrate the first optically enabled UCI chip chiplet uh that was
[49:50] enabled UCI chip chiplet uh that was exciting and there's much coming from
[49:52] exciting and there's much coming from that um for all any of the attendees uh
[49:55] that um for all any of the attendees uh we do offer uh to collaborate and we
[49:57] we do offer uh to collaborate and we want to uh bring forward solutions into
[49:59] want to uh bring forward solutions into this into this
[50:01] this into this realm and I'll hand it back over to you
[50:03] realm and I'll hand it back over to you Jose. Thank you very much Scott and
[50:05] Jose. Thank you very much Scott and congratulation on everything that you
[50:07] congratulation on everything that you are achieving. I'm extremely happy and
[50:10] are achieving. I'm extremely happy and proud that you keep choosing optic as a
[50:12] proud that you keep choosing optic as a platform to make these huge
[50:14] platform to make these huge announcements that shocking the
[50:15] announcements that shocking the industry. There's a few questions for
[50:17] industry. There's a few questions for you, but the first one is coming from
[50:20] you, but the first one is coming from Alexart. He's wondering what kind of
[50:23] Alexart. He's wondering what kind of shoreline density can be achieved with
[50:25] shoreline density can be achieved with the 8 per second solution.
[50:30] Um I I I'm going to reserve I'm going to
[50:33] Um I I I'm going to reserve I'm going to reserve from answering that directly
[50:35] reserve from answering that directly because it really comes down to um pack
[50:37] because it really comes down to um pack packaging
[50:38] packaging approaches. Um now
[50:43] approaches. Um now uh and and that really comes back into
[50:45] uh and and that really comes back into is it is it a single monolithic chiplet?
[50:48] is it is it a single monolithic chiplet? Is it a two-chip solution? Um and it
[50:50] Is it a two-chip solution? Um and it really the answer varies uh depending on
[50:53] really the answer varies uh depending on how you're approaching the packaging uh
[50:55] how you're approaching the packaging uh the packaging packaging challenge and we
[50:58] the packaging packaging challenge and we see customers trying to um um
[51:02] see customers trying to um um approach with different with different
[51:04] approach with different with different packaging approaches and this ties back
[51:06] packaging approaches and this ties back to I think um Vikas and Alex's uh points
[51:09] to I think um Vikas and Alex's uh points on uh the need for standardization on
[51:11] on uh the need for standardization on the packaging uh to today I see it as is
[51:14] the packaging uh to today I see it as is quite fragmented uh people are trying to
[51:16] quite fragmented uh people are trying to figure out what works and what is best
[51:19] figure out what works and what is best for their their applications. So there's
[51:21] for their their applications. So there's no one cookie cutter um answer that I
[51:23] no one cookie cutter um answer that I could give to that question right now. I
[51:26] could give to that question right now. I I think you already gave between the
[51:28] I think you already gave between the lines the answer, but that's okay. Let's
[51:30] lines the answer, but that's okay. Let's go to the next the next question. Like
[51:33] go to the next the next question. Like this one is a visionary question. I
[51:35] this one is a visionary question. I warned you here, Scott. Like electric
[51:38] warned you here, Scott. Like electric power source. Why can't we think about
[51:41] power source. Why can't we think about power box that supplies lambdas to
[51:43] power box that supplies lambdas to boards and racks? and and Shanka is
[51:46] boards and racks? and and Shanka is wondering highdensity laser diode arrays
[51:48] wondering highdensity laser diode arrays are great but they dedicated to a single
[51:50] are great but they dedicated to a single socket or board.
[51:54] socket or board. Jose can you can you can we think about
[51:58] Jose can you can you can we think about your chiplet as a sort of power box that
[52:01] your chiplet as a sort of power box that instead of giving electrical contacts
[52:04] instead of giving electrical contacts provides lambdas to boards a
[52:07] provides lambdas to boards a multi-wavelength solution.
[52:11] multi-wavelength solution. So are we suggesting of uh integrated
[52:14] So are we suggesting of uh integrated lasers? It is a very visionary question.
[52:18] lasers? It is a very visionary question. I think actually we could formulate it
[52:19] I think actually we could formulate it better. Allow me to answer him
[52:22] better. Allow me to answer him privately. But this is is of course more
[52:24] privately. But this is is of course more or less what the interposer solution of
[52:27] or less what the interposer solution of does already. And the last one is from
[52:30] does already. And the last one is from our friend very good friend C person
[52:33] our friend very good friend C person from color chip Brian Hall. Brian Hall
[52:36] from color chip Brian Hall. Brian Hall thank you very much being with us today.
[52:37] thank you very much being with us today. Brian has a difficult question for you,
[52:39] Brian has a difficult question for you, but you have to give us an answer.
[52:40] but you have to give us an answer. Scott, which material is your interposer
[52:43] Scott, which material is your interposer and what is the maximum dimension?
[52:48] I'm going to refrain from answering that
[52:50] I'm going to refrain from answering that one as well. To say glass, you know that
[52:52] one as well. To say glass, you know that it's color chip. Okay, next question.
[52:54] it's color chip. Okay, next question. And are you going to comply with the
[52:57] And are you going to comply with the CWWDM MSA for light source choice? Yes,
[53:00] CWWDM MSA for light source choice? Yes, absolutely. We're an MSA member uh and
[53:03] absolutely. We're an MSA member uh and um very much uh we support that
[53:05] um very much uh we support that standard. people are ask and trying to
[53:08] standard. people are ask and trying to rephrase shanka
[53:10] rephrase shanka question I allow me to answer this in a
[53:13] question I allow me to answer this in a different context because it's a bit a
[53:15] different context because it's a bit a bit visionary present question Scott
[53:18] bit visionary present question Scott what you are doing is really fantastic
[53:20] what you are doing is really fantastic really is I am really proud of having
[53:22] really is I am really proud of having you in the ecosystem congratulations
[53:24] you in the ecosystem congratulations allow me to bring Alexander and Giorgio
[53:26] allow me to bring Alexander and Giorgio back in the room because the next two
[53:28] back in the room because the next two questions are for the two of you all is
[53:31] questions are for the two of you all is wondering what is the typical loss
[53:34] wondering what is the typical loss budget propagation loss us in the fiber
[53:37] budget propagation loss us in the fiber to chip.
[53:41] Alex, do you want to venture a guess
[53:42] Alex, do you want to venture a guess before I say 1 dB?
[53:44] before I say 1 dB? Yes, we have achieved 1 dB. Typically
[53:47] Yes, we have achieved 1 dB. Typically the budget that people are counting
[53:49] the budget that people are counting there's like 2dB for the optical and the
[53:51] there's like 2dB for the optical and the the overall variation but yes the
[53:53] the overall variation but yes the typical uh insertion loss is 1 dB with a
[53:56] typical uh insertion loss is 1 dB with a 2dB budget currently. The other question
[53:59] 2dB budget currently. The other question is about the through glass bias I
[54:02] is about the through glass bias I suppose. Do you typically do routing on
[54:04] suppose. Do you typically do routing on a single layer or do you have solutions
[54:06] a single layer or do you have solutions from layer to layer?
[54:11] Georgio, allow me to get back to you on
[54:13] Georgio, allow me to get back to you on that question. But yes, Georgio, there's
[54:16] that question. But yes, Georgio, there's a question for you on a single layer or
[54:19] a question for you on a single layer or do you have solutions for layer to
[54:21] do you have solutions for layer to layer? Typically is on single layer what
[54:23] layer? Typically is on single layer what we see today. I mean then depends on the
[54:26] we see today. I mean then depends on the evolution but typically single layer.
[54:29] evolution but typically single layer. Single layer is the answer. the answer.
[54:31] Single layer is the answer. the answer. Congratulations and we'll continue with
[54:33] Congratulations and we'll continue with the fantastic program. So far, I'm
[54:34] the fantastic program. So far, I'm really happy things. We are finding out
[54:35] really happy things. We are finding out many interesting things. The next
[54:37] many interesting things. The next speaker is a fantastic speaker. However,
[54:41] speaker is a fantastic speaker. However, he has a fantastic allergy problem. So,
[54:44] he has a fantastic allergy problem. So, he cannot be here today. The company
[54:47] he cannot be here today. The company quantifi is here to help us testing
[54:52] quantifi is here to help us testing chips at ultra high bandwidth. And of
[54:54] chips at ultra high bandwidth. And of course, I would like to wish Case
[54:56] course, I would like to wish Case Popstra from Quantifi Photonix a prom
[54:59] Popstra from Quantifi Photonix a prom recovery. We are missing you today here.
[55:01] recovery. We are missing you today here. Your presentation would have been
[55:02] Your presentation would have been spectacular. I wanted to acknowledge
[55:04] spectacular. I wanted to acknowledge that you were registered for the
[55:05] that you were registered for the meeting. And with that said, let's
[55:07] meeting. And with that said, let's continue and let's go to the final
[55:09] continue and let's go to the final presentation before we do our final
[55:11] presentation before we do our final discussion. I want to go to the company
[55:14] discussion. I want to go to the company Terodine represented today by the senior
[55:17] Terodine represented today by the senior director of SOC product strategy, George
[55:20] director of SOC product strategy, George Harerte. George, thank you very much for
[55:22] Harerte. George, thank you very much for being with us today. The floor and the
[55:24] being with us today. The floor and the attention of everyone goes to our last
[55:26] attention of everyone goes to our last speaker today, Terodine.
[55:30] Thank you,
[55:31] Thank you, Jose. Can you see uh my sharing? Yes.
[55:35] Jose. Can you see uh my sharing? Yes. Yes, we do. Great. Welcome everybody
[55:39] Yes, we do. Great. Welcome everybody again. My name is George Utarte. I am
[55:43] again. My name is George Utarte. I am senior director of product strategy at
[55:45] senior director of product strategy at Pterodine Semiconductor Test. Terodine
[55:48] Pterodine Semiconductor Test. Terodine is in the business of testing the world
[55:51] is in the business of testing the world of
[55:52] of semiconductors from high performance
[55:54] semiconductors from high performance compute devices to power semiconductors
[55:57] compute devices to power semiconductors for electronic electrical vehicles,
[56:00] for electronic electrical vehicles, memory, wireless, we test everything,
[56:02] memory, wireless, we test everything, but we testing high volume. So we're in
[56:05] but we testing high volume. So we're in the business really of prototyping in
[56:08] the business really of prototyping in high
[56:09] high volume semiconductors.
[56:12] volume semiconductors. So my colleagues here in this uh panel
[56:14] So my colleagues here in this uh panel have already explained in different
[56:17] have already explained in different angles from different angles the value
[56:20] angles from different angles the value proposition of silicon photonics or
[56:23] proposition of silicon photonics or photonix IC's I'd like to put things in
[56:26] photonix IC's I'd like to put things in a different perspective clearly the data
[56:29] a different perspective clearly the data centers HPC data centers are shown in
[56:33] centers HPC data centers are shown in this slide are complex not only complex
[56:36] this slide are complex not only complex but they're expensive high cost and the
[56:40] but they're expensive high cost and the key requirements ments for these type of
[56:43] key requirements ments for these type of uh servers clearly high performance high
[56:47] uh servers clearly high performance high relability bandwidth is speed latency
[56:49] relability bandwidth is speed latency power they're expensive they're complex
[56:52] power they're expensive they're complex they need to be reliable in fact they're
[56:55] they need to be reliable in fact they're so expensive that people go serverless
[56:58] so expensive that people go serverless serverless computing meaning renting per
[57:01] serverless computing meaning renting per second this type of systems clearly test
[57:06] second this type of systems clearly test is important we cannot have a new
[57:09] is important we cannot have a new photonix device that goes into the
[57:11] photonix device that goes into the systems fail and then you have to throw
[57:14] systems fail and then you have to throw away a huge system that's not a good
[57:18] away a huge system that's not a good value proposition. So testing testing
[57:20] value proposition. So testing testing testing is important. Terodine gets to
[57:24] testing is important. Terodine gets to basically judge good or bad in terms of
[57:27] basically judge good or bad in terms of the chip and that's a big responsibility
[57:29] the chip and that's a big responsibility because if it is good but it's bad
[57:32] because if it is good but it's bad that's a quality problem a reliability
[57:34] that's a quality problem a reliability problem and if it's bad but it's good
[57:38] problem and if it's bad but it's good and we declare bad but it's good it's a
[57:40] and we declare bad but it's good it's a economical problem we throw away money
[57:42] economical problem we throw away money if I make the point so the value
[57:45] if I make the point so the value proposition of photonics is already
[57:48] proposition of photonics is already explained and we looked at it from
[57:50] explained and we looked at it from different angles right the bandwidth
[57:52] different angles right the bandwidth with advanced packaging, power
[57:55] with advanced packaging, power consumption, space and so on so forth.
[57:58] consumption, space and so on so forth. So you have this slide. I will not go
[58:00] So you have this slide. I will not go through it one more time but it's clear
[58:03] through it one more time but it's clear that it's here to stay for the long run.
[58:06] that it's here to stay for the long run. Let us now define what is an optical
[58:10] Let us now define what is an optical engine and a CPO called package optics.
[58:13] engine and a CPO called package optics. This is important because we need to
[58:15] This is important because we need to define the test insertions that we need
[58:18] define the test insertions that we need to support in the ecosystem to declare a
[58:22] to support in the ecosystem to declare a chip good or no good. And the optical
[58:26] chip good or no good. And the optical engine versus a CPO. The basic
[58:29] engine versus a CPO. The basic difference really is the presence of a
[58:31] difference really is the presence of a compute device. Whether or not it is a
[58:34] compute device. Whether or not it is a switch or in the future perhaps a GPU or
[58:37] switch or in the future perhaps a GPU or XPU. The basic difference is the fact
[58:41] XPU. The basic difference is the fact that we have a switch device or data
[58:44] that we have a switch device or data center which is a really high digital
[58:47] center which is a really high digital device surrounded by multiple
[58:52] device surrounded by multiple transceivers so-called optical engines.
[58:55] transceivers so-called optical engines. So clearly this device which is very
[58:57] So clearly this device which is very expensive surrounded by lower cost type
[59:01] expensive surrounded by lower cost type of optical engines needs to work needs
[59:05] of optical engines needs to work needs to work it and needs to be reliable and
[59:08] to work it and needs to be reliable and a trade-off between throughput and
[59:10] a trade-off between throughput and quality is always important. So here we
[59:13] quality is always important. So here we are now in a simp relatively simple
[59:16] are now in a simp relatively simple optical engine as it relates to the
[59:19] optical engine as it relates to the optical and electrical going into a very
[59:22] optical and electrical going into a very complex type of CPO type of package. So
[59:27] complex type of CPO type of package. So this bring us into the question of what
[59:31] this bring us into the question of what are the possible photonics in this case
[59:34] are the possible photonics in this case silicon photonix and co- package optics
[59:38] silicon photonix and co- package optics test insertions. My colleagues have
[59:41] test insertions. My colleagues have talked a lot about the front end but
[59:44] talked a lot about the front end but they also made a point that the back end
[59:46] they also made a point that the back end needs to be ready in high volume
[59:48] needs to be ready in high volume manufacturing testing and starting with
[59:51] manufacturing testing and starting with the wafer test. There is currently two
[59:54] the wafer test. There is currently two approaches approach in which the
[59:56] approaches approach in which the photonics and the electrical are all in
[01:00:00] photonics and the electrical are all in one side of the wafer. That's one
[01:00:03] one side of the wafer. That's one foundary approach. and the second
[01:00:05] foundary approach. and the second foundary approach in which we bond an
[01:00:07] foundary approach in which we bond an electrical and a photonix. So that means
[01:00:10] electrical and a photonix. So that means that we had to be able to test from both
[01:00:12] that we had to be able to test from both sides top and bottom. That requires a
[01:00:16] sides top and bottom. That requires a high volume probing solution and
[01:00:19] high volume probing solution and alignment solution to be able to make
[01:00:21] alignment solution to be able to make contacts both electrically and in the
[01:00:25] contacts both electrically and in the optical side. Then there is a question
[01:00:28] optical side. Then there is a question is do we singulate the die and test it
[01:00:31] is do we singulate the die and test it at the die? That is an important
[01:00:34] at the die? That is an important question that uh we are obviously in the
[01:00:37] question that uh we are obviously in the process of as an ecosystem answering and
[01:00:40] process of as an ecosystem answering and the reason this is an important question
[01:00:42] the reason this is an important question is when we go to the CPU module this is
[01:00:46] is when we go to the CPU module this is very expensive we cannot throw away you
[01:00:49] very expensive we cannot throw away you know 2 $3,000 type of chip or higher in
[01:00:53] know 2 $3,000 type of chip or higher in the in the case of basically pluggable
[01:00:56] the in the case of basically pluggable modules the cost of a pluggable module
[01:01:00] modules the cost of a pluggable module compared to the cost of integrating
[01:01:03] compared to the cost of integrating the optical engine in the switch making
[01:01:06] the optical engine in the switch making a CPO a significant orders of magnitude
[01:01:09] a CPO a significant orders of magnitude different perhaps when we win the
[01:01:11] different perhaps when we win the optical pluggable module here will be a
[01:01:14] optical pluggable module here will be a more like a throwaway if it fails well
[01:01:17] more like a throwaway if it fails well replace the cable the fiber cable
[01:01:19] replace the cable the fiber cable replace the two ends so to speak of the
[01:01:22] replace the two ends so to speak of the entire cable with the pluggable module
[01:01:23] entire cable with the pluggable module so you're done but we cannot throw away
[01:01:26] so you're done but we cannot throw away and replace the CPU module that would be
[01:01:29] and replace the CPU module that would be too expensive not economical and
[01:01:31] too expensive not economical and basically really a wall to high volume
[01:01:35] basically really a wall to high volume manufacturing or CPO. So we got to be
[01:01:38] manufacturing or CPO. So we got to be thinking you know what is to be tested
[01:01:40] thinking you know what is to be tested in the automatic test equipment one is
[01:01:42] in the automatic test equipment one is to be get tested perhaps on the circuit
[01:01:44] to be get tested perhaps on the circuit level and then at the end what goes into
[01:01:47] level and then at the end what goes into the AT or SLT and there is multiple uh
[01:01:51] the AT or SLT and there is multiple uh test that need to be done. Main point we
[01:01:55] test that need to be done. Main point we got to have non good die before we put
[01:01:58] got to have non good die before we put this into the CPO. So that brings the
[01:02:02] this into the CPO. So that brings the challenges you know in the old days so
[01:02:04] challenges you know in the old days so to speak maybe two three years ago in
[01:02:07] to speak maybe two three years ago in lower volume you know some of these
[01:02:10] lower volume you know some of these challenges were you know uh let's say
[01:02:13] challenges were you know uh let's say tolerable but now we got to find
[01:02:16] tolerable but now we got to find solutions at the wafer level for example
[01:02:19] solutions at the wafer level for example not only we had to test optical and
[01:02:21] not only we had to test optical and electrical signals but this point here
[01:02:24] electrical signals but this point here of aligning aligning the optical fiber
[01:02:28] of aligning aligning the optical fiber with a wafer is significant
[01:02:31] with a wafer is significant Just aligning the laser source to the
[01:02:34] Just aligning the laser source to the optical to the to the photonics I see
[01:02:38] optical to the to the photonics I see used to take
[01:02:39] used to take minutes many minutes and the other two
[01:02:42] minutes many minutes and the other two digit minutes needs to go into one to
[01:02:45] digit minutes needs to go into one to two minutes less into the seconds to be
[01:02:48] two minutes less into the seconds to be able to make a manufacturer. So you know
[01:02:51] able to make a manufacturer. So you know companies like FContech who are doing
[01:02:53] companies like FContech who are doing the alignment mechanisms you are key to
[01:02:57] the alignment mechanisms you are key to be able to reduce the throughput to to
[01:02:59] be able to reduce the throughput to to improve the throughput so to speak to uh
[01:03:02] improve the throughput so to speak to uh increase the throughput that is of uh
[01:03:05] increase the throughput that is of uh this type of alignment mechanisms. I
[01:03:07] this type of alignment mechanisms. I already talked about double-sided
[01:03:09] already talked about double-sided program then there is the highspeed
[01:03:11] program then there is the highspeed digital photonix testing you know that
[01:03:14] digital photonix testing you know that is continuously screening. So we need to
[01:03:17] is continuously screening. So we need to bring photonix instrumentation into the
[01:03:19] bring photonix instrumentation into the at side and the ST side. And then
[01:03:22] at side and the ST side. And then there's thermal management. I show you
[01:03:24] there's thermal management. I show you the anatomy of the of the chassis right
[01:03:27] the anatomy of the of the chassis right of the of the data server. You have
[01:03:29] of the of the data server. You have cooling lines coming in. All of that. So
[01:03:31] cooling lines coming in. All of that. So that is at at the end all of those
[01:03:34] that is at at the end all of those things need to be addressed as we go
[01:03:36] things need to be addressed as we go into testing. So continuing with the
[01:03:40] into testing. So continuing with the test challenges there is there was a
[01:03:43] test challenges there is there was a question earlier today about
[01:03:44] question earlier today about standardization.
[01:03:46] standardization. the CPO connector could be an
[01:03:48] the CPO connector could be an opportunity. is an opportunity for
[01:03:50] opportunity. is an opportunity for standardization because we had to align
[01:03:52] standardization because we had to align in high volume production the way the
[01:03:55] in high volume production the way the the light source to the CPO connectors
[01:03:58] the light source to the CPO connectors and we have multiple connectors then it
[01:04:00] and we have multiple connectors then it becomes not economical that's an area
[01:04:03] becomes not economical that's an area for a standardization can we really
[01:04:05] for a standardization can we really standardize a connector to be able to
[01:04:08] standardize a connector to be able to have a more high volume economical
[01:04:12] have a more high volume economical solution so there's different type of
[01:04:15] solution so there's different type of applications or or challenges but I want
[01:04:17] applications or or challenges but I want to highlight do alignment alignment
[01:04:20] to highlight do alignment alignment alignment of the light source with the
[01:04:24] alignment of the light source with the wafer with the optical engine with the
[01:04:27] wafer with the optical engine with the CPO. That is absolutely key and an area
[01:04:30] CPO. That is absolutely key and an area to resolve and the other one is the
[01:04:33] to resolve and the other one is the integration of optical instrumentation
[01:04:36] integration of optical instrumentation into the traditionally heavy electrical
[01:04:38] into the traditionally heavy electrical type of test. So therefore, Terodine a
[01:04:42] type of test. So therefore, Terodine a leader in high volume manufacturing and
[01:04:45] leader in high volume manufacturing and test. We have partnered with companies
[01:04:49] test. We have partnered with companies like for example uh Fon Fontest
[01:04:54] like for example uh Fon Fontest uh uh Font Tech. uh recently we
[01:04:56] uh uh Font Tech. uh recently we announced at the end of March that the
[01:04:59] announced at the end of March that the collaboration and innovation with
[01:05:02] collaboration and innovation with partnerships like Font Tech enables us
[01:05:04] partnerships like Font Tech enables us to deliver first high volume
[01:05:07] to deliver first high volume double-sided test cell for silicon photo
[01:05:10] double-sided test cell for silicon photo test. So we believe that this
[01:05:12] test. So we believe that this collaboration is key. That's one area
[01:05:15] collaboration is key. That's one area related to alignment double-sided. We
[01:05:18] related to alignment double-sided. We also recognize the importance of
[01:05:20] also recognize the importance of bringing photonics testing to the AT
[01:05:23] bringing photonics testing to the AT that has been traditionally electrical.
[01:05:26] that has been traditionally electrical. So we have announced the acquisition of
[01:05:28] So we have announced the acquisition of quantified photonics as well to be able
[01:05:32] quantified photonics as well to be able to bring this new capability into the AT
[01:05:36] to bring this new capability into the AT and eventually gives us a path to reduce
[01:05:39] and eventually gives us a path to reduce the footprint of an AT test cell by
[01:05:42] the footprint of an AT test cell by bringing platonics instrumentation at
[01:05:45] bringing platonics instrumentation at some point inside the tester head rather
[01:05:48] some point inside the tester head rather than externally. So with all of these
[01:05:51] than externally. So with all of these type of uh innovations and collaboration
[01:05:54] type of uh innovations and collaboration in the industry, we believe that
[01:05:56] in the industry, we believe that terodine is well positioned well
[01:05:59] terodine is well positioned well positioned to enable high volume
[01:06:03] positioned to enable high volume botonics not only on the optical engine
[01:06:06] botonics not only on the optical engine side but also on the silicon into the
[01:06:09] side but also on the silicon into the co- package optic CPO side for data
[01:06:13] co- package optic CPO side for data centers. So thank you very much for
[01:06:15] centers. So thank you very much for listening. We'll take some questions
[01:06:16] listening. We'll take some questions next. Thank you very much George. It was
[01:06:18] next. Thank you very much George. It was very clear for me at OFC that the major
[01:06:21] very clear for me at OFC that the major challenge for the hyperscalers to keep
[01:06:23] challenge for the hyperscalers to keep integrating silicon photonics or
[01:06:25] integrating silicon photonics or photonic iterative circuits is that they
[01:06:27] photonic iterative circuits is that they have doubts about the reliability. It is
[01:06:30] have doubts about the reliability. It is what it is. They have doubts and we can
[01:06:32] what it is. They have doubts and we can only convince them with data. It was
[01:06:35] only convince them with data. It was clear in the presentation by Scott that
[01:06:38] clear in the presentation by Scott that he's talking about no good die but
[01:06:41] he's talking about no good die but actually we should actually rephrase
[01:06:42] actually we should actually rephrase that into no bad die because we actually
[01:06:46] that into no bad die because we actually have to make sure that every device is
[01:06:47] have to make sure that every device is tested when they leave when they leave
[01:06:50] tested when they leave when they leave Jable. How we going to do this? Are we
[01:06:53] Jable. How we going to do this? Are we doing you are focusing on wafer level
[01:06:54] doing you are focusing on wafer level testing die testing and package device
[01:06:57] testing die testing and package device testing? Is it necessary today in your
[01:07:00] testing? Is it necessary today in your opinion to test and characterize every
[01:07:03] opinion to test and characterize every single chip die and packaged model and
[01:07:06] single chip die and packaged model and if that's if that is the solution is
[01:07:09] if that's if that is the solution is that economically feasible
[01:07:12] that economically feasible so as every new inflection point in
[01:07:15] so as every new inflection point in technology in the history right we
[01:07:18] technology in the history right we initially start the conservative side I
[01:07:21] initially start the conservative side I made a point right that this data center
[01:07:24] made a point right that this data center CPO and its chassis cost thousands of
[01:07:27] CPO and its chassis cost thousands of dollars so we cannot not risk when there
[01:07:29] dollars so we cannot not risk when there is a new
[01:07:30] is a new technology just being adopted. We cannot
[01:07:33] technology just being adopted. We cannot risk uh losing economically. So we start
[01:07:36] risk uh losing economically. So we start conservative. We start characterizing at
[01:07:38] conservative. We start characterizing at the wafer level the mechanic in this
[01:07:40] the wafer level the mechanic in this case electrical plus photonics. So we
[01:07:42] case electrical plus photonics. So we means we have to provide the
[01:07:43] means we have to provide the instrumentation at the wafer level you
[01:07:46] instrumentation at the wafer level you know to be able to characterize it.
[01:07:48] know to be able to characterize it. Question is on the die package and
[01:07:50] Question is on the die package and eventually we go into the package. So
[01:07:52] eventually we go into the package. So what happens is as we learn and volume
[01:07:54] what happens is as we learn and volume increase we start scaling down so to
[01:07:57] increase we start scaling down so to speak or removing certain tests are
[01:07:59] speak or removing certain tests are perhaps not needed because failures
[01:08:02] perhaps not needed because failures don't happen often or at all maybe was
[01:08:04] don't happen often or at all maybe was going to lube back testing versus actual
[01:08:07] going to lube back testing versus actual at speed testing. So there is an
[01:08:09] at speed testing. So there is an evolution that takes uh you know several
[01:08:11] evolution that takes uh you know several years until we hit the sweet spot of a
[01:08:14] years until we hit the sweet spot of a balance between test coverage being cost
[01:08:16] balance between test coverage being cost of test also and equality. So cost of
[01:08:19] of test also and equality. So cost of test and cost of quality need to be
[01:08:21] test and cost of quality need to be balanced but that takes a an evolution.
[01:08:24] balanced but that takes a an evolution. So it's a learning curve. Initially we
[01:08:26] So it's a learning curve. Initially we tend to provide the maximum test
[01:08:28] tend to provide the maximum test coverage at the beginning and eventually
[01:08:31] coverage at the beginning and eventually we optimize it. We have two very good
[01:08:34] we optimize it. We have two very good questions for you here in the Q&A
[01:08:35] questions for you here in the Q&A button. The first one is coming from
[01:08:37] button. The first one is coming from Alina Stefan. You've been talking about
[01:08:39] Alina Stefan. You've been talking about alignment. Alignment alignment as the
[01:08:41] alignment. Alignment alignment as the biggest challenge and she's wondering do
[01:08:43] biggest challenge and she's wondering do you have experts in alignment?
[01:08:47] you have experts in alignment? So, Terodine's strategy is to
[01:08:50] So, Terodine's strategy is to collaborate with the best of the best in
[01:08:53] collaborate with the best of the best in the industry ecosystem. There are
[01:08:56] the industry ecosystem. There are companies out there like Fontest Tech,
[01:08:59] companies out there like Fontest Tech, FCON Tech and others who are experts in
[01:09:02] FCON Tech and others who are experts in alignment for many years, you know. So,
[01:09:04] alignment for many years, you know. So, so we are in the business of providing
[01:09:06] so we are in the business of providing the
[01:09:08] the at equipment that can interface with the
[01:09:11] at equipment that can interface with the best of the best on the test cell. So,
[01:09:14] best of the best on the test cell. So, if we find a company like FCON Tech who
[01:09:16] if we find a company like FCON Tech who are the experts, we partner with them.
[01:09:18] are the experts, we partner with them. That's why we did the announcement. That
[01:09:20] That's why we did the announcement. That doesn't mean that we internally don't
[01:09:22] doesn't mean that we internally don't also develop expertise to understand how
[01:09:25] also develop expertise to understand how to partner with them you know to speak
[01:09:27] to partner with them you know to speak the language of the font text. We
[01:09:28] the language of the font text. We understand we need understand alignment
[01:09:30] understand we need understand alignment technology. So of course you know we
[01:09:32] technology. So of course you know we will get mechanical engineers we get
[01:09:34] will get mechanical engineers we get alignment people who can understand how
[01:09:36] alignment people who can understand how to develop together with the best of
[01:09:39] to develop together with the best of base on the ecosystem. The next question
[01:09:42] base on the ecosystem. The next question in the room comes from light counting
[01:09:44] in the room comes from light counting Bob willer what about infield
[01:09:47] Bob willer what about infield reliability says this is a huge barrier
[01:09:50] reliability says this is a huge barrier for CPU adoption and he didn't hear any
[01:09:52] for CPU adoption and he didn't hear any mention.
[01:09:54] mention. Yeah. So I I I did touch on that when I
[01:09:58] Yeah. So I I I did touch on that when I saw the data center anatomy, right? That
[01:10:00] saw the data center anatomy, right? That chassis and I mentioned that reliability
[01:10:02] chassis and I mentioned that reliability is important and that's a field
[01:10:04] is important and that's a field reliability and that was in the context
[01:10:06] reliability and that was in the context of making the point that we need the
[01:10:08] of making the point that we need the best test coverage starting for wafer
[01:10:11] best test coverage starting for wafer pro. I think my colleagues made that
[01:10:12] pro. I think my colleagues made that point. The more test coverage we can put
[01:10:15] point. The more test coverage we can put early in the process, you know, we'll be
[01:10:17] early in the process, you know, we'll be able to to uh to guaranteed reliability.
[01:10:20] able to to uh to guaranteed reliability. Now the other question is burning. you
[01:10:22] Now the other question is burning. you know do we do burning photonics I think
[01:10:24] know do we do burning photonics I think there is a trend also to to bring uh
[01:10:27] there is a trend also to to bring uh some level of burning into the photonic
[01:10:30] some level of burning into the photonic site uh for for this type of devices so
[01:10:33] site uh for for this type of devices so we can screen out uh early uh
[01:10:36] we can screen out uh early uh reliability issues
[01:10:38] reliability issues the next question h this one is coming
[01:10:40] the next question h this one is coming from te connectivity these guys know
[01:10:42] from te connectivity these guys know what they're talking about he's asking
[01:10:44] what they're talking about he's asking you to talk a little about passive
[01:10:46] you to talk a little about passive versus active alignment and he's
[01:10:49] versus active alignment and he's wondering and I'm wondering the same
[01:10:51] wondering and I'm wondering the same actually is passive alignment possible
[01:10:53] actually is passive alignment possible in CBO.
[01:10:58] Yeah, that's uh still an evolving
[01:11:01] Yeah, that's uh still an evolving question, right? That uh allow allow me
[01:11:03] question, right? That uh allow allow me to venture and answer my I I believe I
[01:11:06] to venture and answer my I I believe I firmly believe that the future of
[01:11:08] firmly believe that the future of photonix is
[01:11:10] photonix is semiconductorbased manufacturing and
[01:11:12] semiconductorbased manufacturing and semiconductor manufacturing has been
[01:11:14] semiconductor manufacturing has been based for many years on passive
[01:11:16] based for many years on passive alignment. The reason we have to do
[01:11:18] alignment. The reason we have to do active alignment is because we need to
[01:11:20] active alignment is because we need to test components individually and we need
[01:11:22] test components individually and we need to test optically those components and
[01:11:24] to test optically those components and of course for that we need to put fibers
[01:11:26] of course for that we need to put fibers and detectors next to the facets and
[01:11:28] and detectors next to the facets and that can only be done actively. However,
[01:11:30] that can only be done actively. However, as a technology becomes more mature and
[01:11:32] as a technology becomes more mature and in the case of CPO this is going to
[01:11:34] in the case of CPO this is going to happen. I don't expect us to be able to
[01:11:37] happen. I don't expect us to be able to optically test every single fiber input
[01:11:40] optically test every single fiber input in 128 fiber arrays. So I believe the
[01:11:44] in 128 fiber arrays. So I believe the future is passive alignment. However,
[01:11:46] future is passive alignment. However, active alignment is necessary for as
[01:11:48] active alignment is necessary for as long as we have not reliable and not
[01:11:50] long as we have not reliable and not 100% yield in our wafers. That's my
[01:11:52] 100% yield in our wafers. That's my venture guess. And with that, uh, we
[01:11:57] venture guess. And with that, uh, we have a question for we have a question
[01:12:00] have a question for we have a question for global
[01:12:03] foundaries. Uh, no it's not. It's a is
[01:12:06] foundaries. Uh, no it's not. It's a is GF photonics a software tool for silicon
[01:12:08] GF photonics a software tool for silicon photonic devices designed for
[01:12:10] photonic devices designed for manufacturing? Allow me to answer that
[01:12:12] manufacturing? Allow me to answer that offline. And I would like to say now to
[01:12:14] offline. And I would like to say now to to George, to Vicas, to Scott, to
[01:12:18] to George, to Vicas, to Scott, to Georgio, to Alexander, to Nick, and of
[01:12:21] Georgio, to Alexander, to Nick, and of course to the Advanced Phutonics
[01:12:23] course to the Advanced Phutonics Coalition. Thank you for a fantastic one
[01:12:26] Coalition. Thank you for a fantastic one hour of a quarter of entertainment,
[01:12:30] hour of a quarter of entertainment, knowledge, and most important business
[01:12:31] knowledge, and most important business and collaboration. If I had to say what
[01:12:33] and collaboration. If I had to say what is the conclusion for me for this
[01:12:35] is the conclusion for me for this business is that we all need to work
[01:12:38] business is that we all need to work together because you can see that many
[01:12:40] together because you can see that many people here in the room had fantastic
[01:12:43] people here in the room had fantastic technology but no one had the full
[01:12:46] technology but no one had the full solution and we all need to work
[01:12:48] solution and we all need to work together because our customers demand
[01:12:50] together because our customers demand that today. Thank you very much
[01:12:52] that today. Thank you very much everyone. This was Jose Posto run by a
[01:12:54] everyone. This was Jose Posto run by a group of friends. Until the next time,
[01:12:58] bye-bye.
[01:13:07] [Music]
[01:13:14] Heat. Heat.
[01:13:17] Heat. Heat. [Music]

https://www.youtube.com/watch?v=oSMUz-hy-LE

Summary

TL;DR — The AI revolution is driving an unprecedented demand for data center traffic, necessitating robust manufacturing of Photonic Integrated Circuits (PICs). This webinar brings together key players across the value chain to discuss challenges and solutions in scaling PIC production for AI applications.

Key points

• The Advanced Photonics Coalition (APC) is working to standardize and lower barriers for new PIC technologies, with active working groups on silicon photonics, multi-core fiber, core package optics, and optical waveguide interconnects.

• Foundries like Global Foundries are developing flexible platforms (GFotonix) and wafer-level processing techniques to enable high-volume, cost-effective manufacturing of PICs.

• Advanced packaging solutions, including co-packaged optics (CPO), are crucial for bridging the gap between compute and interconnect bandwidth, with IBM highlighting breakthroughs in high-density optical interconnects.

• Contract manufacturers like Jabil are essential for scaling production, focusing on reducing time-to-market and ensuring robust manufacturing processes through automation and standardization.

• Companies like Ayar Labs are developing novel optical chiplets, such as the 8 Tb/s UCI chiplet, pushing the boundaries of bandwidth and requiring integrated laser sources and advanced packaging.

• Testing is a critical enabler for reliability, with Teradyne and others focusing on wafer-level, die-level, and package-level testing, including optical and electrical characterization, to ensure known good die for CPO integration.

Takeaway — Collaboration across the entire PIC ecosystem, from design and manufacturing to packaging and testing, is essential to meet the demands of the AI revolution and enable robust, high-volume production.