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Co-Packaged Optics – 3D Heterogeneous Integration of Photonic IC and Electronic IC

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This lecture discusses co-packaged optics (CPO), a technology that integrates photonic integrated circuits (PICs) and electronic integrated circuits (EICs) onto a single substrate for high-performance computing and data centers. It explores various 3D heterogeneous integration methods, focusing on advancements beyond traditional on-board optics and near-package optics, and highlights the challenges and opportunities in scaling these technologies, particularly with the emergence of glass substrates.

Full Transcript

https://www.youtube.com/watch?v=7t-ku1LJb_U

[00:04] In the next 1 hour and 50 minutes, I would like to share with you what I learned about cold package objects.
[00:19] This lecture is sponsored by ITLE EPS.
[00:31] EPS by the way my email is there.
[00:37] You have the presentation fire do you?
[00:45] No. No. Where is organized? Yeah.
[00:49] Send them the presentation fire.
[00:52] You have any question email me I will respond you.
[00:55] Okay. So this is started by EPS please read
[01:06] It. This is the content of my talk.
[01:15] Silicon photonic.
[01:17] You used this terminology photonic.
[01:20] You used this terminology before, did you?
[01:24] Before, did you?
[01:28] Yeah. Many of my friends they like to talk about silicon.
[01:33] And they even say they are working on silicon.
[01:36] But they don't even have a fact.
[01:43] They say they are working on silicon.
[01:49] Silicon.
[01:52] Silicon photonic is the integration of IC and photonic on a silicon vapor.
[01:59] So silicon photonic is for
[02:09] Vapor. So silicon photonic is for silicon interpretations.
[02:12] Silicon interpretations. So on the way you integrate the icing.
[02:17] So on the way you integrate the icing and the photonics by similar technology.
[02:22] It is very difficult in the whole wide world.
[02:26] The only company who is in high volume production on silicon is only India.
[02:30] TSMC 10 years ago they make the announcement we will not work on silicon performing.
[02:39] So from now on they use the terminology silicon component.
[02:50] So from now on they use the terminology silicon component.
[02:56] So from now on they use the terminology silicon component.
[02:58] Yeah. That is silicon photonic on a piece of paper. You
[03:10] Photonic on a piece of paper.
[03:13] You integrate the IC and integrate the IC and photonics by single.
[03:26] Single.
[03:26] Today I will only talk about code package of this which is by packing network to integrate the photonic IC and the electronic IC on the same subm.
[03:52] Product of product of people of packaging people.
[04:00] People.
[04:00] So whole package of things is historic of the PIC and EIC on the same.
[04:15] historic of the PIC and EIC on the same substrate.
[04:17] We call that whole package subject.
[04:26] Everyone everybody got it?
[04:31] Okay.
[04:34] If you are looking for civic photonic, this is not for you.
[04:40] I am talking by method to integrate the photonic acid and the electronic IC that is all okay.
[04:59] So what is the advantage of so CPO?
[05:07] There are at least three
[05:17] advantage.
[05:21] One, oh this is a LED so laser doesn't work.
[05:26] One is to increase the electrical performance to reduce the power to enhance the the electrical performance.
[05:38] Okay.
[05:42] So very clear I will only talk about histois integration of photonic IC and electrical IC.
[06:00] also what I'm talking about is not for mobile device like a smartphone because what I'm talking about is too much for that.
[06:13] Okay, it is not application for
[06:17] that.
[06:19] Okay, it is not application for those mobile those mobile device.
[06:24] What I'm talking is about data center high performance computing products driven by a deficient integrity.
[06:38] So today the data center is on your left you have the switch you have all the powerful transceiver 90% today the data center those transceiver are pable however in the future on your right hand side it will be co- package of this it will have a switch with 16 optical engine those optical engine will have
[07:20] engine those optical engine will have the PIC such as a driver
[07:25] the PIC such as a driver TIA until the laser and the photo
[07:30] TIA until the laser and the photo detectors and the EIC such as uh laser
[07:35] detectors and the EIC such as uh laser driver and the
[07:45] TIA.
[07:47] TIA.
[07:50] I make up this to share with you what the industry is doing.
[07:59] First one is fable.
[08:06] fable. That means the shrink with the substrate on the center
[08:11] shrink with the substrate on the center of the substrate.
[08:13] On the four sides of the substrate, you will have the
[08:22] Substrate, you will have the transceiver.
[08:24] That's what we are doing today.
[08:26] 95% data set is this technology.
[08:31] Six years ago, people say why don't you try on board optics.
[08:39] On both artistics is to move the transceiver from the X of the substrate to all sides of the A6 string.
[08:48] Boom.
[08:54] This is a big improvement.
[09:02] The signal delay is reduced.
[09:05] So by moving the transceiver from the edge to the interior of the port around the edge of the A6.
[09:26] the edge of the A6 subject is a big improvement.
[09:29] subject is a big improvement.
[09:29] We call it on board optics.
[09:37] OB about five years ago people say let's.
[09:41] OB about five years ago people say let's do a little bit.
[09:44] do a little bit better which is.
[09:47] better which is near package of.
[09:50] near package of the.
[09:54] NPO which is to use a substrate.
[09:59] NPO which is to use a substrate to support the pace.
[10:03] to support the pace shrink and the optical.
[10:08] engine.
[10:12] That is a step improvement from OBO.
[10:16] improvement from OBO.
[10:16] cost than industry one.
[10:20] cost than industry one or on uh co package.
[10:25] or on uh co package optic which.
[10:27] optic which is to move all the optical.
[10:32] is to move all the optical engine side by side with the async.
[10:37] engine side by side with the async switch as switch on the same.
[10:41] sub. This is what we call cold package.
[10:47] sub. This is what we call cold package substrate.
[10:50] On the same substrate you have the as shrink.
[10:53] shrink. Right next to it you have the optical.
[10:56] optical agent. This is called cold.
[10:58] agent. This is called cold package.
[11:02] Today only detail and bottle.
[11:07] package. Today only detail and bottle they are doing.
[11:09] Oh, by the way, this is our pack.
[11:13] way, this is our pack.
[11:16] Okay, so this shows you the AS6 streak side by side with the electronic IC and the photonic IC.
[11:22] streak side by side with the electronic IC and the photonic IC.
[11:26] they are on a
[11:32] IC and the photonic IC.
[11:34] They are on an organic interposer and then on the package.
[11:37] Interposer and then on the package substrate and then on the PC substrate and then on the PC board.
[11:40] Okay.
[11:43] Board. Okay.
[11:43] So this is both package of this.
[11:59] How to make the organic interposer?
[12:03] I mean, I mean, this how to make the organic interposer?
[12:14] There are two ways.
[12:25] One. By the way, there are two ways to make it for both ways.
[12:28] One. By the way, there are two ways to make it for both ways.
[12:29] You have to make the package.
[12:36] Ways. You have to make the package substrate and the organic interposer.
[12:42] Substrate and the organic interposer.
[12:47] Second, after that there are two ways to go.
[12:48] One is to assembly the organic eoser on the buildup substrate to make sure it is a good hybrid substrate and then you found the AC CP and BIC that's one way.
[13:16] The other way most of the people do is after you make the organic interposer and you are suffer you by the sweet PIC EIC on the organic poster.
[13:40] EIC on the organic poster first and first and then assembly on the you are.
[13:47] then assembly on the you are suffering.
[13:50] So there are two ways to suffering.
[13:50] So there are two ways to do.
[13:56] Okay.
[13:56] I prefer the first way.
[14:01] You make the organic interoser.
[14:05] You make the build up suffering.
[14:11] You find the organic interoser in the build up suffering.
[14:15] and then test it.
[14:21] Make sure it is a good hybrid soft and then you bound the switch, you bound the PIC, you bound the EIC.
[14:34] I prefer this way and my company can do it very well.
[14:37] By the way,
[14:42] company can do it very well.
[14:42] By the way, my company is a PC shop.
[14:47] We make PC board.
[14:49] Okay.
[14:49] So, we can make the success.
[14:53] We can make the organic income poster.
[14:58] We together and test it.
[15:03] Make sure it is a good hybrid and then we ship it.
[15:08] The old set just pick up the asex sw and b on the hybrid side.
[15:17] p.
[15:22] Okay.
[15:22] So that's why I prefer the to the organic composer or the bum package substrate first and test it and make sure it is a good hybrid substrate.
[15:44] Make sure it is a good hybrid substrate and ship it to the so one.
[15:53] The so one is make the organic is make the organic interposer bound the chip and then do interposer bound the chip and then do the the assembly.
[16:06] Another one the one I like which is to combine the organic interoser on the build of suffering.
[16:13] Interoser on the build of suffering. Make sure it is a good one and then ship it to the OAP and then OSAP bound the switch PIC EIC on the no good hybrid stuff.
[16:34] I'm going to skip some of this.
[16:38] Stuff. I'm going to skip some of this.
[16:40] Please read it yourself. If you have some questions, please ask me. This is
[16:44] Some questions, please ask me.
[16:45] This is our applications.
[16:47] Applications.
[16:47] Okay.
[16:50] So, please read it.
[16:52] Okay.
[16:56] In they ship their product which is the A6 is on the center and then you have 16 optical engines.
[17:07] Broadcom also shoot their cold package optics.
[17:11] Okay, again you have the switch and then you have 16 optical engines.
[17:21] Everything is fine that is for 25.6.
[17:26] 6 30 bits per second.
[17:35] But next generation is 51 30 bits per
[17:46] 51 30 bits per second.
[17:46] But the form factor is the same.
[17:52] second.
[17:52] But the form factor is the same.
[17:52] So the tactic of the industry face a problem.
[17:59] problem.
[18:00] because the optical engine the size will because the optical engine the size will be increased.
[18:05] be increased.
[18:06] Those 16 optical engine increased.
[18:10] Those 16 optical engine around the street the size around the street the size increase but the street size is the increase but the street size is the same.
[18:14] increase but the street size is the same.
[18:19] So what can we same.
[18:22] So what can we do?
[18:29] Well, one way is to set up the PIC and DIC and you can place the optical entry on the substrate.
[18:31] and DIC and you can place the optical entry on the substrate.
[18:37] on the substrate.
[18:40] For example, we stack up the
[18:46] example, we stack up the EIC on top of the EIC on top of the PIC PIC with organic interposer.
[18:58] interposer. So in this case the substrate can support everybody.
[19:08] everybody. That's why I call it 3D hystogenouses integration of PIC and EIC.
[19:20] Okay. Yeah. This is some of our tech. So this is what I give you today.
[19:29] How to set up the PIC on the EIC.
[19:36] So you can put it on the same put it on the same substrate.
[19:47] That means you increase in the vertical.
[19:53] That means you increase in the vertical space but you still can keep the space.
[19:58] but you still can keep the horizontal space the horizontal space the same.
[20:02] same. Okay.
[20:04] Okay. So these are the 11.
[20:08] So these are the 11 different.
[20:10] different 3D pistol genesis.
[20:13] 3D pistol genesis integration of PIC and.
[20:18] integration of PIC and EIC. Okay.
[20:23] So I go through it one by one with you.
[20:48] Okay. Oh, this doesn't work.
[20:51] Okay. Oh, this doesn't work. The first one is to stack up the EIC on
[20:57] The first one is to stack up the EIC on the
[20:58] the PIC by
[21:01] PIC by microb and then the signal is coming out
[21:06] microb and then the signal is coming out from the Y bar on the
[21:09] from the Y bar on the PIC to the next level of
[21:16] interconnect and the signal is coming
[21:20] interconnect and the signal is coming from the Bible to the
[21:24] from the Bible to the PIC. This is first one.
[21:30] The second one, the signal is coming
[21:34] The second one, the signal is coming from a fiber to the
[21:37] from a fiber to the PIC and then the PIC is connected to the
[21:42] PIC and then the PIC is connected to the EIC with the micro
[21:45] EIC with the micro bump and the signal is coming out from
[21:50] bump and the signal is coming out from the C4 bump to the next level for in the
[21:59] country. The third case is very popular
[22:04] country. The third case is very popular in research lab today.
[22:08] in research lab today. The third one is to set up the EIC on
[22:14] The third one is to set up the EIC on the
[22:15] the PIC and the signal coming in from the
[22:19] PIC and the signal coming in from the fiber to the
[22:21] fiber to the PIC and the EIC and PIC is
[22:27] PIC and the EIC and PIC is interconnected with
[22:29] interconnected with microb soal C2
[22:33] microb soal C2 B also called
[22:36] B also called clearer with solder
[22:39] clearer with solder t.
[22:41] t. Okay. And then the EIC is with
[22:46] Okay. And then the EIC is with GSV through silicon
[22:51] GSV through silicon via and then micro bump to the next
[22:56] via and then micro bump to the next level of interact.
[23:02] The fourth
[23:03] The fourth case
[23:05] case is EIC attack to
[23:11] is EIC attack to PIC but not with micro
[23:14] PIC but not with micro pump is
[23:17] pump is with to copper hydro pumping.
[23:27] The fifth
[23:29] The fifth case
[23:31] case is the
[23:34] is the EIC attached to the
[23:37] EIC attached to the PIC through a PS3
[23:53] intersected to PIC.
[23:56] intersected to PIC. See, we replace the T3
[24:01] See, we replace the T3 interposer to organic
[24:07] interposer.
[24:09] interposer. HG the signal coming from the fiber to
[24:14] HG the signal coming from the fiber to the
[24:15] the PIC and then microbump on the TSV
[24:20] PIC and then microbump on the TSV interoser and then microbump to EIC.
[24:25] interoser and then microbump to EIC. And the signal is coming from the
[24:29] And the signal is coming from the microbump to the next level of
[24:34] microbump to the next level of interpreter. P8 is basically the same
[24:40] interpreter. P8 is basically the same except I replace the T3
[24:44] except I replace the T3 interosure to organic interosion.
[24:50] Case nine is basically the same except I
[24:56] Case nine is basically the same except I replace the
[24:58] replace the microb
[24:59] microb into copper to copper hybrid bonding.
[25:07] Case
[25:08] Case 10 is the signal coming from the fiber
[25:14] 10 is the signal coming from the fiber to
[25:15] to PIC and then micro bump on the subframe
[25:21] PIC and then micro bump on the subframe and then the
[25:23] and then the EIC is with sort of bump on the package
[25:29] EIC is with sort of bump on the package subframe. So this is package on
[25:35] subframe. So this is package on package. Case 11 also is package on
[25:42] package. Case 11 also is package on package except the
[25:46] package except the EIC is not on the package software.
[25:52] EIC is not on the package software. The EIC is B out and
[25:59] The EIC is B out and that deposit volume.
[26:04] So I give you 11 different
[26:07] So I give you 11 different cases to stack up the
[26:11] cases to stack up the PIC with
[26:14] PIC with EIC with C4
[26:18] EIC with C4 bump C2 bump which is micro
[26:23] bump C2 bump which is micro bump and copper to copper hybrid
[26:29] bump and copper to copper hybrid bounty
[26:31] bounty plus TS3
[26:34] plus TS3 through silicon
[26:36] through silicon via
[26:40] interposes.
[26:41] interposes. Okay. So I encourage
[26:45] Okay. So I encourage you to look at
[26:48] you to look at this and
[26:50] this and then
[26:52] then think maybe there are some
[26:57] think maybe there are some other
[26:59] other technical structures.
[27:05] There will be
[27:07] There will be artists apply for a
[27:10] artists apply for a captain with your
[27:12] captain with your name. No, I'm serious. Okay, I give you
[27:16] name. No, I'm serious. Okay, I give you 11 days. You can think
[27:19] 11 days. You can think hard different
[27:23] hard different technically. Okay.
[27:31] So because my proposal here involve C4
[27:37] So because my proposal here involve C4 bump, C2 bump, tier three
[27:42] bump, C2 bump, tier three and to couple hybrid bumping. So each
[27:48] and to couple hybrid bumping. So each one I will very
[27:52] one I will very simply mention to
[27:55] simply mention to you. Oh, by the way before that this is
[28:00] you. Oh, by the way before that this is Cisco's
[28:03] Cisco's paper. This our case
[28:06] paper. This our case three. The EIC is on top of the PIC with
[28:12] three. The EIC is on top of the PIC with micro bump and then with TS3 on the
[28:17] micro bump and then with TS3 on the substrate. This is our case three.
[28:25] This is by sphere published a few months
[28:29] This is by sphere published a few months ago. They use stand out to embed the
[28:35] ago. They use stand out to embed the application
[28:39] processor in
[28:45] the
[28:46] the EIC. So this is
[28:52] our past came. Okay.
[28:57] our past came. Okay. So people are you see okay there I'm
[29:01] So people are you see okay there I'm very
[29:06] happy as I
[29:08] happy as I said all this stacking up 3D needs C4
[29:14] said all this stacking up 3D needs C4 bump C2 bump here three
[29:19] bump C2 bump here three and to copper hybrid
[29:23] and to copper hybrid bumping
[29:26] So this is how I feel the train
[29:32] So this is how I feel the train on C4 B the
[29:36] on C4 B the sol and the cup with solder t the rifle
[29:44] sol and the cup with solder t the rifle bomb.
[29:47] bomb. Today most of the people use C4 bump is
[29:53] Today most of the people use C4 bump is 100 m
[29:56] 100 m diameter 150 micron
[29:59] diameter 150 micron pitch. Some people using 50
[30:03] pitch. Some people using 50 micron diameter sort of bump and 100
[30:08] micron diameter sort of bump and 100 micron pitch.
[30:10] micron pitch. In
[30:12] In laboratory some people doing study by
[30:17] laboratory some people doing study by using 25 micron sum and 50
[30:25] micron on the copper so called the C2
[30:31] micron on the copper so called the C2 bump today most of the people use 50
[30:36] bump today most of the people use 50 micron
[30:38] micron papa and 100 bon pitch with solid
[30:45] papa and 100 bon pitch with solid cap. Some people are using 25 micron
[30:51] cap. Some people are using 25 micron diameter carpet and 50 micron pitch.
[30:57] diameter carpet and 50 micron pitch. Some
[30:58] Some laboratory they are doing research with
[31:02] laboratory they are doing research with 10 micron
[31:05] 10 micron micro
[31:07] micro papira with 20
[31:12] micro smaller than
[31:15] micro smaller than that. No
[31:18] that. No cup, no
[31:21] cup, no solar cup
[31:24] solar cup and another bear copper
[31:31] so
[31:35] hybrid anybody here working
[31:39] on I know but anyone here working
[31:43] on I know but anyone here working on top I
[31:47] on top I Anyway, not in huh not
[31:59] ins you know there is a conference
[32:02] ins you know there is a conference called
[32:04] called ECTC everybody
[32:07] ECTC everybody know that is the direction for packaging
[32:13] know that is the direction for packaging the best packaging conference on
[32:16] the best packaging conference on earth every year
[32:21] in you know last
[32:24] in you know last year the whole
[32:27] year the whole conference how many came on
[32:33] top how many you want to
[32:38] guess how
[32:40] guess how many how
[32:45] Huh?
[32:47] Huh? 100. No, not that
[32:50] 100. No, not that day.
[32:52] day. 82. A
[32:54] 82. A whole
[32:56] whole 82. Nothing
[33:00] 82. Nothing but hybrid.
[33:06] The year
[33:08] The year before how we
[33:10] before how we live
[33:13] live 78 and the year before
[33:16] 78 and the year before that
[33:17] that 72 now this year I don't know how
[33:21] 72 now this year I don't know how many I have to wait until
[33:28] May. Okay. So I'm no
[33:39] focus. Uh this is how to do way pumping.
[33:44] focus. Uh this is how to do way pumping. Please read it yourself.
[33:53] Okay. This the hybrid
[33:55] Okay. This the hybrid part. Okay. Please read it yourself. Uh
[34:00] part. Okay. Please read it yourself. Uh if you have question please email me.
[34:15] Okay.
[34:19] Everyone in
[34:22] Everyone in packaging you heard about a
[34:26] packaging you heard about a terminology called bridges.
[34:31] Yeah. Huh? Silicon bridge.
[34:34] Yeah. Huh? Silicon bridge. Yeah. Silicon bridge. Very good. Who
[34:37] Yeah. Silicon bridge. Very good. Who else? You email. Yes. Who else?
[34:44] Now bridge is a very very important
[34:51] Now bridge is a very very important technology for chip and
[35:00] pistol.
[35:02] pistol. Bridges is a tiny piece of silicon. No
[35:11] device only RBL and
[35:15] device only RBL and TSV
[35:17] TSV connecting two different
[35:21] connecting two different chip that's why is so important as you
[35:24] chip that's why is so important as you know chiplet is the game
[35:27] know chiplet is the game today
[35:29] today and the way to connect the chiplet is
[35:35] and the way to connect the chiplet is bricks and Today most of the
[35:39] bricks and Today most of the bridges as a matter of fact all the
[35:42] bridges as a matter of fact all the bridges use
[35:45] bridges use microb for example
[35:48] microb for example Intel's
[35:50] Intel's EMI IBM's
[35:53] EMI IBM's everybody they use my home to connect
[35:58] everybody they use my home to connect the bridges
[36:07] This is our
[36:10] This is our pattern. We
[36:12] pattern. We use
[36:13] use buckets cut to copper hybrid
[36:18] buckets cut to copper hybrid bonding connecting the silicon bridge in
[36:22] bonding connecting the silicon bridge in the
[36:23] the chip. No bomb. No more
[36:31] bomb. Two weeks
[36:34] bomb. Two weeks ago, according to the industry industry
[36:40] ago, according to the industry industry news, the
[36:43] news, the computer
[36:47] M5 M5 has been
[36:50] M5 M5 has been using bridges. with Michael
[36:55] using bridges. with Michael B. Two weeks
[36:57] B. Two weeks ago they made the
[37:01] ago they made the announcement their
[37:04] announcement their bridges will be using
[37:08] bridges will be using TSMC's
[37:10] TSMC's SOIC. Now,
[37:13] SOIC. Now, SIC is the core and butter of GSMC
[37:21] SIC is the core and butter of GSMC technology. SIC simply speaking
[37:26] technology. SIC simply speaking is couple to couple hybrid B.
[37:32] is couple to couple hybrid B. So before end of this year when you open
[37:36] So before end of this year when you open up Apple computer notebook their M5
[37:41] up Apple computer notebook their M5 connected to F5 with the bridge will
[37:46] connected to F5 with the bridge will be to copper
[37:50] hybrid let's
[37:55] see how to make a
[37:58] see how to make a TSV of because it takes all day to talk
[38:01] TSV of because it takes all day to talk about it. So I simply show you this one.
[38:05] about it. So I simply show you this one. So please read it. If you have any
[38:08] So please read it. If you have any question, please email
[38:13] me. Yeah, this how to make a TSV. How to
[38:18] me. Yeah, this how to make a TSV. How to make a redistri layer on top of the TSV.
[38:23] make a redistri layer on top of the TSV. This is the paper we published
[38:26] This is the paper we published uh 13 years ago. And so please read
[38:31] uh 13 years ago. And so please read this. All these are
[38:35] this. All these are necessary for those 11 cases I
[38:42] necessary for those 11 cases I mentioned. These are the enabling
[38:50] technology. Okay.
[38:53] technology. Okay. Now I stack up the PIC on
[38:57] Now I stack up the PIC on EIC.
[39:00] EIC. Okay. So this is not called whole
[39:05] Okay. So this is not called whole package of this
[39:08] package of this yet. Wait
[39:11] yet. Wait until
[39:13] until second and then put it side by side with
[39:19] second and then put it side by side with the asent string.
[39:22] the asent string. on the same
[39:24] on the same substrate can be we call it total
[39:28] substrate can be we call it total package optic
[39:31] package optic sub. Okay. So now I I have many cases.
[39:38] sub. Okay. So now I I have many cases. The first one is the stack up of the EIC
[39:43] The first one is the stack up of the EIC on PIC side by side with the switch on
[39:47] on PIC side by side with the switch on the cold package substrate. Okay.
[39:52] the cold package substrate. Okay. Or the cold package substract can be CSV
[39:59] Or the cold package substract can be CSV interposer or organic
[40:08] interposer. I make some of
[40:12] interposer. I make some of those when I put the strip and the
[40:18] those when I put the strip and the 3D pic EIC on the
[40:24] 3D pic EIC on the substrate. I can use the bridges to
[40:28] substrate. I can use the bridges to enhance the performance.
[40:32] enhance the performance. For
[40:35] example, I can use a silicon
[40:39] example, I can use a silicon bridge connecting the
[40:42] bridge connecting the PIC with the asex
[40:45] PIC with the asex switch or I can use Intel's
[40:50] switch or I can use Intel's EMIB and data in the package
[40:54] EMIB and data in the package substrate connecting the PIC and
[40:59] substrate connecting the PIC and EIC or I and embed the silicon bridge in
[41:05] EIC or I and embed the silicon bridge in the fan
[41:07] the fan outing compound with redistribution
[41:12] outing compound with redistribution layer. You can use
[41:17] many as long
[41:20] many as long as the switch and the PIC and
[41:25] as the switch and the PIC and EIC they are side by side on a single
[41:33] EIC they are side by side on a single subject. By the way, this is the
[41:36] subject. By the way, this is the definition of
[41:39] definition of historicis integration. You
[41:42] historicis integration. You see the definition of disco geniuses
[41:46] see the definition of disco geniuses integration is to have different chip on
[41:50] integration is to have different chip on the same
[42:01] subject. I have my taxi wait meeting
[42:05] subject. I have my taxi wait meeting waiting for me at 1:15.
[42:30] this example. Okay. Finally
[42:35] this example. Okay. Finally is this is for a product driven by
[42:39] is this is for a product driven by artificial
[42:41] artificial intelligent. You have the graphic
[42:44] intelligent. You have the graphic processor supported by the high
[42:47] processor supported by the high bandwidth memory and then on the
[42:51] bandwidth memory and then on the substrate you have the optical
[42:54] substrate you have the optical engine. It's not in production yet.
[42:58] engine. It's not in production yet. Okay, this is my
[43:00] Okay, this is my imagination
[43:02] imagination but it will
[43:04] but it will happen. Okay,
[43:07] happen. Okay, so on the co pack cold package subject
[43:12] so on the co pack cold package subject you have the GPU you have the high
[43:15] you have the GPU you have the high banded memory and you have the optical
[43:19] banded memory and you have the optical engine connecting the fiber to the
[43:22] engine connecting the fiber to the outside world.
[43:26] So I make it more complicated so we can
[43:30] So I make it more complicated so we can apply more patterns.
[43:34] apply more patterns. So the
[43:36] So the GPU is connecting with the streak with
[43:41] GPU is connecting with the streak with the optical
[43:43] the optical agent. So on your right hand side this
[43:48] agent. So on your right hand side this is what we have been talking
[43:50] is what we have been talking about. On your left hand side is for the
[43:55] about. On your left hand side is for the GPU applies to the product driven by
[44:01] GPU applies to the product driven by artificial
[44:03] artificial intelligence. They can combine with the
[44:06] intelligence. They can combine with the B and work together. I think three to
[44:11] B and work together. I think three to five years if
[44:13] five years if you of course
[44:17] you of course maybe years
[44:21] So this is our
[44:26] purpose and then all this component are
[44:30] purpose and then all this component are on the code package subject and then on
[44:34] on the code package subject and then on the build up package subject and then on
[44:42] PC. Okay.
[44:46] PC. Okay. glass
[44:47] glass of
[44:49] of everybody got
[44:50] everybody got excited when Intel Smith made the
[44:54] excited when Intel Smith made the announcement on September September 18,
[45:00] announcement on September September 18, 2023. Everybody know that? No. Yeah,
[45:04] 2023. Everybody know that? No. Yeah, some of you
[45:06] some of you know suddenly everybody is crazy about
[45:11] know suddenly everybody is crazy about fast
[45:14] subject. Last year I went to China to do
[45:17] subject. Last year I went to China to do a
[45:19] a lecture. I find out there are more than
[45:22] lecture. I find out there are more than 100 companies working on
[45:28] that. They did not read the last paraple
[45:35] that. They did not read the last paraple of the announcement.
[45:44] This is the inapp
[45:48] announcement about the
[45:57] use. Oh, this is the last last sentence.
[46:04] use. Oh, this is the last last sentence. Their class is for one trillion
[46:09] Their class is for one trillion transistor on the
[46:13] process. My friend, do you know what is
[46:17] process. My friend, do you know what is one trillion transistor
[46:20] one trillion transistor means?
[46:23] No. Your iPhone. I don't have a phone. I
[46:27] No. Your iPhone. I don't have a phone. I never use a phone. But my daughter's
[46:33] never use a phone. But my daughter's iPhone last
[46:36] iPhone last October. You know how many transistor
[46:39] October. You know how many transistor are there? 20 millions. Ah 20 millions.
[46:42] are there? 20 millions. Ah 20 millions. Yeah. 20 billion. This is one trillion.
[46:48] So
[46:50] So God's suffering is for very niche of
[46:56] God's suffering is for very niche of this. Last year I went to China. Wow.
[47:00] this. Last year I went to China. Wow. Many people come to me. There are more
[47:03] Many people come to me. There are more than 100 company they are doing nothing
[47:06] than 100 company they are doing nothing but
[47:08] but gas. I'm wondering what's their
[47:11] gas. I'm wondering what's their application.
[47:14] So glass is for niche
[47:20] So glass is for niche application. This is their panel. The
[47:23] application. This is their panel. The size is
[47:24] size is 510 by
[47:26] 510 by 515. So this is the panel size of our
[47:30] 515. So this is the panel size of our company. We have a manufacturing line.
[47:34] company. We have a manufacturing line. We can make the organic
[47:37] We can make the organic interpose down to two micron light bit
[47:41] interpose down to two micron light bit and spacing. I mean two micro light and
[47:45] and spacing. I mean two micro light and spacing by PC technology. We have a
[47:50] spacing by PC technology. We have a manufacturing like seven
[47:53] manufacturing like seven years. We also have a glass
[48:00] have
[48:03] sent the panel size the same 510 by
[48:14] 550. So for their one trillion
[48:19] 550. So for their one trillion transistor they say to replace the
[48:23] transistor they say to replace the organic core into glass core.
[48:33] There are many advantage please reading.
[48:45] So we are also under
[48:52] pressure. But we
[48:55] pressure. But we know glass is for nature
[48:59] know glass is for nature application and we also
[49:07] know the advantage.
[49:11] know the advantage. eight higher ability to seamless
[49:16] eight higher ability to seamless integrate optical
[49:19] integrate optical interconnect. So our
[49:22] interconnect. So our attention is only applied
[49:27] attention is only applied to
[49:29] to optical the glass
[49:33] sub. So this our first
[49:41] vacation to integrate the EIC on PIC
[49:48] vacation to integrate the EIC on PIC with a glass
[49:52] with a glass interposer. The glass
[49:55] interposer. The glass interposer is with
[49:59] interposer is with TGV through glass V.
[50:08] So we apply patent for
[50:12] So we apply patent for this two years
[50:14] this two years ago. No, not two years, one and a half
[50:18] ago. No, not two years, one and a half years ago after September
[50:22] years ago after September 18, 2023.
[50:31] So we set up the EIC on
[50:35] So we set up the EIC on PIC with a class
[50:42] interposer. We apply another
[50:46] interposer. We apply another pattern which is to embed the
[50:51] pattern which is to embed the PIC in a glass subject.
[50:56] PIC in a glass subject. Why do we do that?
[50:59] Why do we do that? Because on the glass substrate
[51:04] Because on the glass substrate surface we can make the glass way down
[51:09] surface we can make the glass way down which is connecting to the signal coming
[51:14] which is connecting to the signal coming from outside the
[51:17] from outside the Bible. That's why we use gas to make the
[51:22] Bible. That's why we use gas to make the glass way
[51:24] glass way down. One end is connecting to the
[51:28] down. One end is connecting to the photonic IC. The other end is connecting
[51:32] photonic IC. The other end is connecting to the
[51:36] fiber. Yeah, this is our
[51:39] fiber. Yeah, this is our patent
[51:41] patent and the EIC or the PIC is with copper to
[51:50] and the EIC or the PIC is with copper to copper.
[51:52] copper. This one is with C2
[51:56] bond. Next one is with copper to copper
[52:02] bond. Next one is with copper to copper hybrid
[52:04] hybrid bonding. So this is how we
[52:08] bonding. So this is how we see the glass
[52:12] see the glass substate come into
[52:15] substate come into picture. Okay. Detail is for one tree
[52:22] picture. Okay. Detail is for one tree application
[52:24] application process. We are using the glass sub
[52:31] for package of
[52:35] for package of this. Okay.
[52:39] These are how to make it
[52:46] this. Of course, they are also
[52:57] trying. This is the last thing I'm going
[53:00] trying. This is the last thing I'm going to give it to
[53:01] to give it to you.
[53:03] you. Of course
[53:05] Of course today no one talk about the
[53:09] today no one talk about the reliability because of the
[53:12] reliability because of the subject. Okay. No
[53:16] subject. Okay. No one.
[53:18] one. So we publish a
[53:22] So we publish a paper to tell
[53:24] paper to tell you because of the god
[53:33] subject there is a
[53:35] subject there is a problem with what the industry is doing.
[53:42] Okay. On your right hand
[53:45] Okay. On your right hand side. On your right hand
[53:53] side. On your right hand side.
[53:58] side. On your right hand side. You have the
[54:01] You have the conventional suffering which is with
[54:06] conventional suffering which is with organic build up and then supporting the
[54:10] organic build up and then supporting the chip. This is what we have been
[54:13] chip. This is what we have been doing
[54:15] doing for 30
[54:21] years. So on the right hand side this is
[54:25] years. So on the right hand side this is what we have been doing for the past 30
[54:33] years. One and a half years
[54:35] years. One and a half years ago inel proposed to replace the organic
[54:41] ago inel proposed to replace the organic core with the
[54:47] glass for their application process.
[54:57] Now this is the key.
[55:04] The
[55:06] The goal the CPE is very
[55:10] goal the CPE is very low because the people make the CP of
[55:17] low because the people make the CP of gas as close as to the
[55:23] gas as close as to the silicon because chips is not on top. So
[55:26] silicon because chips is not on top. So they make the
[55:29] they make the CTE or the gas called as close as to the
[55:35] CTE or the gas called as close as to the silicon. Silicon is
[55:39] silicon. Silicon is 2.5 they make it
[55:41] 2.5 they make it into six 4.8
[55:48] 8 and the organic pole we use today is
[55:54] 8 and the organic pole we use today is about
[56:00] 10.
[56:02] 10. Also please
[56:07] know the chip the fifth chip on the
[56:13] know the chip the fifth chip on the substrate
[56:15] substrate always under is that right?
[56:23] Yes.
[56:25] Yes. find the sort of bump on PC
[56:33] board. So we have two kinds of bump. One
[56:37] board. So we have two kinds of bump. One is the micro bump supporting the chip.
[56:41] is the micro bump supporting the chip. One is C4 bump on the PC board.
[56:48] The C4 pump we also call it PG
[56:55] The C4 pump we also call it PG A on
[56:58] A on his no
[57:01] his no under. Is that
[57:04] under. Is that right? Because under field is not
[57:09] right? Because under field is not reworkable on the large PC board. If
[57:13] reworkable on the large PC board. If something wrong with the chip, the whole
[57:16] something wrong with the chip, the whole thing need to take out. But if you use
[57:20] thing need to take out. But if you use under field for the C4 bump, you cannot
[57:24] under field for the C4 bump, you cannot remove the whole B has to throw
[57:29] remove the whole B has to throw away. But the under B under the
[57:33] away. But the under B under the chin use under
[57:36] chin use under pill. If the chip is dead just
[57:42] [Music]
[57:48] reflect the whole board you still can
[57:55] use.
[57:56] use. So what I'm going to show
[58:01] So what I'm going to show is because the
[58:04] is because the CTE
[58:06] CTE of the that
[58:10] of the that subject is closer to the CTE of the
[58:15] subject is closer to the CTE of the check.
[58:19] The micro sort of thumb is okay as it
[58:23] The micro sort of thumb is okay as it has the under field
[58:26] has the under field production.
[58:30] However, the thermal expansion
[58:35] However, the thermal expansion mismatch between the glass
[58:39] mismatch between the glass substrate and the PC
[58:42] substrate and the PC board increase. Is that right?
[58:46] board increase. Is that right? Because all the people when they select
[58:50] Because all the people when they select the CTE or class, they want to use it as
[58:56] the CTE or class, they want to use it as close to the silicon chip as possible to
[59:02] close to the silicon chip as possible to make it as small as
[59:05] make it as small as possible. Then the thermal expensive
[59:09] possible. Then the thermal expensive mismatch between the PC board and the
[59:13] mismatch between the PC board and the glass is left.
[59:18] Then the solder joint the C4 B of the
[59:23] Then the solder joint the C4 B of the solder joint
[59:26] solder joint is in
[59:28] is in question because of the large thermal
[59:31] question because of the large thermal expansion
[59:33] expansion mist that's why I wrote I wrote this
[59:37] mist that's why I wrote I wrote this paper telling the whole wide world the
[59:41] paper telling the whole wide world the industry is heading into the
[59:47] industry is heading into the long they should increase the city
[59:52] long they should increase the city of the glass
[59:56] of the glass subject because there is under field
[59:59] subject because there is under field projection. The micro bomb should be
[01:00:04] projection. The micro bomb should be okay but the thermal expansion we made
[01:00:10] okay but the thermal expansion we made between the glass and the PC board will
[01:00:14] between the glass and the PC board will be
[01:00:15] be reduced. Then the strength and strength
[01:00:20] reduced. Then the strength and strength in the C4 solder joint will be
[01:00:28] in the C4 solder joint will be reliable. Everybody got it?
[01:00:42] So, please bring it. We're going to do
[01:00:46] So, please bring it. We're going to do it here. You may feel bored about
[01:00:57] this. Okay.
[01:01:00] this. Okay. I have 10 minutes left. I will let you
[01:01:04] I have 10 minutes left. I will let you ask me question. I'm going to skip all
[01:01:07] ask me question. I'm going to skip all this.
[01:01:09] this. Please read it. If you have any
[01:01:11] Please read it. If you have any questions, please email
[01:01:30] me. I propose
[01:01:34] me. I propose some culture.
[01:01:40] The first one is I propose in heaven
[01:01:44] The first one is I propose in heaven there. There must be
[01:01:47] there. There must be more. Use your
[01:01:51] more. Use your imagination
[01:01:53] imagination to create
[01:01:56] to create more than a high
[01:02:02] for on the class
[01:02:06] for on the class subject.
[01:02:09] subject. Again, use your
[01:02:13] Again, use your imagination to
[01:02:15] imagination to discover some of the
[01:02:18] discover some of the structure
[01:02:20] structure effectively use the glass subject.
[01:02:32] and talk about different stack of PIC,
[01:02:37] and talk about different stack of PIC, EIC or EIC
[01:02:41] EIC or EIC pic. I did not talk about a very very
[01:02:47] pic. I did not talk about a very very very important topic when you stand up.
[01:02:52] very important topic when you stand up. I
[01:02:53] I see which
[01:02:55] see which is how to take it out before it
[01:03:02] is how to take it out before it affect the electrical
[01:03:08] and
[01:03:11] and polity to take the heat out.
[01:03:14] polity to take the heat out. This is a very very big
[01:03:18] This is a very very big problem, very very good
[01:03:21] problem, very very good opportunity for us to do thermal
[01:03:26] opportunity for us to do thermal management of 3D integration of PIC and
[01:03:34] management of 3D integration of PIC and EIC. I truly mean okay even though I do
[01:03:38] EIC. I truly mean okay even though I do I did not fall but it is a very very
[01:03:42] I did not fall but it is a very very important
[01:03:45] problem the other reason I did
[01:03:49] problem the other reason I did not is because I did not
[01:03:52] not is because I did not work and in the
[01:03:55] work and in the future there is
[01:03:58] future there is nothing on the whole
[01:04:03] nothing on the whole package So it is your
[01:04:09] opportunity. There are many
[01:04:13] interconnect the C4
[01:04:16] interconnect the C4 bomb. So sol
[01:04:20] bomb. So sol reliability is the big power and it's a
[01:04:24] reliability is the big power and it's a good
[01:04:27] opportunity. Uh these are some of my
[01:04:30] opportunity. Uh these are some of my recent
[01:04:32] recent publications by the way.
[01:04:34] publications by the way. If you are DPS member, you can download
[01:04:39] If you are DPS member, you can download it for
[01:04:41] it for free as much as you like.
[01:04:47] Okay, these are my
[01:04:50] Okay, these are my books. Now I have 10 minutes left.
[01:04:55] books. Now I have 10 minutes left. Please ask question.
[01:05:07] Yes.
[01:05:15] Good.
[01:05:24] All kinds of you.
[01:05:32] [Music]
[01:06:01] I guess just bypass is not enough
[01:06:06] I guess just bypass is not enough because the bigness of polymer is
[01:06:10] because the bigness of polymer is very so just by it is not enough. So the
[01:06:14] very so just by it is not enough. So the last subject is
[01:06:17] last subject is about the money.
[01:06:23] Next question.
[01:06:44] How to do a optical recovery is our
[01:06:49] How to do a optical recovery is our scope of my lecture today.
[01:06:55] I don't think he's not he is very very
[01:06:59] I don't think he's not he is very very important
[01:07:06] but that's
[01:07:24] talk anyone use different layer of
[01:07:28] talk anyone use different layer of glasses.
[01:07:32] Yeah. No, I
[01:07:33] Yeah. No, I never but it's possible. That's what I
[01:07:37] never but it's possible. That's what I mean. Use your imagination. Yeah. I
[01:07:42] mean. Use your imagination. Yeah. I never thought
[01:07:53] All things
[01:08:05] [Music]
[01:08:18] Oh, so you make the campus
[01:08:22] Oh, so you make the campus You put the diet in a B state and then
[01:08:27] You put the diet in a B state and then you put the PIC and then make
[01:08:31] you put the PIC and then make FL you know you have the D and B stage
[01:08:36] FL you know you have the D and B stage and then you can pass it as the PC in
[01:08:42] and then you can pass it as the PC in the
[01:08:44] the class. Yes. Next question.
[01:08:56] No. Okay. Thank you very much.

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