# 2025 OCP APAC Summit Keynote - ASE

https://www.youtube.com/watch?v=PMb2OfiLeIM

[00:01] Please welcome AS's executive vice.
[00:04] Please welcome AS's executive vice president, Yin Chang.
[00:22] Good morning.
[00:24] Good morning.
[00:24] First, I want to thank Open Compute Platform for the kind invitation to AAC to share a brief vision of us doing advanced packaging, doing this very interesting era of AI.
[00:43] AI is here.
[00:47] We all know that AI is in every part of our life from health care to communication to e-commerce and financial services.
[00:55] For Hawaii was AI economy for something less than $200 billion just a few years ago is projected to see almost $5
[01:03] ago is projected to see almost $5 trillion by 2033.
[01:08] trillion by 2033.
[01:08] A 25fold increase in such a short amount of time.
[01:11] And with this AI explosion, the data growth is also growing exponentially to almost 200 gigabyte.
[01:17] 200 gigabyte.
[01:17] And this will propel the global GDP to maintain a 15% growth from today to 2030.
[01:25] global GDP to maintain a 15% growth from today to 2030.
[01:27] And this is the importance of AI to us.
[01:30] There are multiple AI models as you probably already aware and previous presenter has shared.
[01:33] There are multiple AI models as you probably already aware and previous presenter has shared.
[01:35] There's multimodal AI.
[01:38] Um this is the generative AI that can be put into probably a robotic system quite soon.
[01:42] can be put into probably a robotic system quite soon.
[01:45] So we are probably going to do do five senses of human from audio to visual to possibly taste, smell and touch.
[01:48] So we are probably going to do do five senses of human from audio to visual to possibly taste, smell and touch.
[01:56] And then the most recent thing about a genic AI which the proactive AI is going to be upon us that
[02:00] And then the most recent thing about a genic AI which the proactive AI is going to be upon us that
[02:05] proactive AI is going to be upon us that can reason learn and act on our behalf.
[02:09] can reason learn and act on our behalf based on our performances pre.
[02:11] based on our performances pre preferences and desires and all this AI.
[02:15] preferences and desires and all this AI require compute tremendous amount of.
[02:18] require compute tremendous amount of compute power and this is a challenge.
[02:20] compute power and this is a challenge that semiconductor industry faces the.
[02:23] that semiconductor industry faces the performance are increasing at 2 to 7x.
[02:26] performance are increasing at 2 to 7x every year.
[02:28] every year. require much more memory bandwidth and.
[02:31] require much more memory bandwidth and require two time to 10x of network.
[02:34] require two time to 10x of network bandwidth just on memory alone. So to.
[02:37] bandwidth just on memory alone. So to put more memory to put more SOC we need.
[02:40] put more memory to put more SOC we need to increase this area size of modules.
[02:43] to increase this area size of modules from today of three retical size could.
[02:45] from today of three retical size could be as big as 10 reticle size in 2027.
[02:49] be as big as 10 reticle size in 2027. So how do we drive all these silicon? We.
[02:52] So how do we drive all these silicon? We need now consider power. How do you.
[02:55] need now consider power. How do you reduce power losses? How to increase.
[02:58] reduce power losses? How to increase power efficiencies? And with this much.
[03:00] power efficiencies? And with this much power, thermal becomes the next.
[03:03] power, thermal becomes the next challenge for us to reduce the thermal.
[03:06] challenge for us to reduce the thermal requirement for every AI system.
[03:11] requirement for every AI system.
[03:13] So this kind of show very simply the left chart shows how various models increasing the data set by almost 4x every year does require the compute to grow as fast.
[03:26] But how do we do that in today's semiconductor challenges?
[03:28] And this is one of the challenges for us.
[03:31] Next is memory.
[03:35] So to feed all the SOC's and all the chiplets, we need the memory to grow with it.
[03:40] But as you see it very clearly in the chart, the black line is where the compute is growing, accelerating, and the green line is where the HVM is.
[03:51] There is a gap.
[03:54] So we are now end up putting more memory per chiplets or per the SOC architecture and this grows the area of the modules.
[04:02] So you kind of see the HPC HVM road map where if you look at AMD the latest
[04:08] where if you look at AMD the latest Nvidia Blackwell or Ruben by 2027?
[04:12] Nvidia Blackwell or Ruben by 2027 they'll grow number of HVM from today's.
[04:15] they'll grow number of HVM from today's eight HVM per modules to 16 HVM per modules in HVM4.
[04:20] and this is what driving the challenges for us as a assembly company to create larger larger area and create more efficiency and utilization.
[04:32] efficiency and utilization. for every interposer that we use.
[04:35] So if you look at where the key challenges for large-siz modules today we're running basically 10,000 square millimeter of module 100 by 100 millimeter modules and that continue to grow and that's a already a 5x retical size and we plan to see from some of the customer as much as 10 reticle size in the very near future.
[04:59] and this is all the challenges with regarding warpage regarding utilization of the panels yield deals get reduced as a panel get bigger and these are the.
[05:08] a panel get bigger and these are the challenges that we face.
[05:12] But to deliver challenges that we face.
[05:15] But to deliver the power to drive all these large modules with 16 HBMs and 11 chiplets,
[05:19] the power delivery challenges is no longer just afterthought.
[05:22] is a number one thing for us to try to figure out to improve the power efficiency and to reduce the power loss as the current increases.
[05:36] Now if you look at thermal requirements this chart kind of quickly identify the challenge that we see.
[05:39] If you look at the red and green chart where the CPU and GPU uh current would be driving by 2030 GPU will be running at 1500 watt and CPU doing 500 watts right but to run these type of power the temperature for the devices actually need to be lower need
[06:08] devices actually need to be lower need to be around 30° C compared today air.
[06:12] to be around 30° C compared today air cool you might to run at 50 60°.
[06:14] cool you might to run at 50 60° So this is another thermal challenges.
[06:16] So this is another thermal challenges for us as part of the overall.
[06:18] for us as part of the overall semiconductor supply chain.
[06:21] How do we solve such problems?
[06:23] solve such problems?
[06:26] So this is the innovation ecosystem that ASC strive to share with the open.
[06:29] ASC strive to share with the open compute platform through new materials.
[06:32] compute platform through new materials possibly new development and new.
[06:34] possibly new development and new equipments.
[06:36] equipments. And those are all leveraging our heterogeneous solutions that help us.
[06:39] our heterogeneous solutions that help us with co- package optic that allow us to.
[06:43] with co- package optic that allow us to do less and less power or more efficiently.
[06:45] do less and less power or more efficiently.
[06:48] efficiently. So our goal is actually always to do.
[06:50] So our goal is actually always to do more than more.
[06:54] more than more. If you hear earlier the power of compute require 4x per year is.
[06:57] power of compute require 4x per year is significantly faster growth than what.
[06:59] significantly faster growth than what Morrisol has shared with us in the past.
[07:01] Morrisol has shared with us in the past 20 years.
[07:04] 20 years. So we're pushing a limit of architecture semiconductor.
[07:07] architecture semiconductor packaging solution and all this thing.
[07:10] packaging solution and all this thing has to done with a lower cost or at no cost increase.
[07:13] has to done with a lower cost or at no cost increase and this require more new efficiencies.
[07:18] efficiencies.
[07:18] So what does AAC would like to do?
[07:21] AAC want to leverage the VIP pack that we introduced back in late 2022.
[07:24] It's vertical integrated package that we start out with focus a fan out package with chip last chip first solution.
[07:29] Now we're doing full production on focus bridge with silicone bridge solution and then we're going on to two and a half to 3D IC's not to mention also co- package optic.
[07:39] So all these are typically tools that allow silicon architect, AI architect, data center architect to create the new innovation breakthrough that allow us to reach those compute power that we all seek to have.
[07:57] So first is talk about focus and focus is basically allow us to do organic RDL on top of glass carriers that connect
[08:11] on top of glass carriers that connect chiplets possibly HVN together but with chiplets possibly HVN together but with HBM bandwidth requirements we're now putting a silicon bridge the silicon
[08:17] HBM bandwidth requirements we're now putting a silicon bridge the silicon bridge interposer are sitting most
[08:19] putting a silicon bridge the silicon bridge interposer are sitting most likely between a HBM3 or HBM4 and you
[08:22] bridge interposer are sitting most likely between a HBM3 or HBM4 and you know a chiplet solution and running a C4 bump less than 130 microns.
[08:26] know a chiplet solution and running a C4 bump less than 130 microns.
[08:34] So we talked about earlier the size of the module is very very important.
[08:37] So we talked about earlier the size of the module is very very important.
[08:40] the module is very very important. So at 5x retical size there's only seven module per 300 millimeter wafers and
[08:42] 5x retical size there's only seven module per 300 millimeter wafers and that's only 57% utilization.
[08:45] module per 300 millimeter wafers and that's only 57% utilization. So AAC is looking at larger panel sizes, 300 millimeter panel and 600 millimeter panels and that allow us to use up to 87% utilization for a 5x retical size package.
[08:49] that's only 57% utilization. So AAC is looking at larger panel sizes, 300 millimeter panel and 600 millimeter panels and that allow us to use up to 87% utilization for a 5x retical size package.
[08:52] looking at larger panel sizes, 300 millimeter panel and 600 millimeter panels and that allow us to use up to 87% utilization for a 5x retical size package.
[08:54] millimeter panel and 600 millimeter panels and that allow us to use up to 87% utilization for a 5x retical size package.
[08:57] panels and that allow us to use up to 87% utilization for a 5x retical size package.
[09:01] 87% utilization for a 5x retical size package.
[09:03] package. So this is an example of that. This is a 10 die with 10 silicon bridges onto a panel format.
[09:07] So this is an example of that. This is a 10 die with 10 silicon bridges onto a panel format.
[09:10] 10 die with 10 silicon bridges onto a panel format. So is 10 eight comput with
[09:16] panel format.
[09:16] So is 10 eight comput with two IO silicon that are connected by 10
[09:19] two IO silicon that are connected by 10 bridge dice.
[09:22] So it kind of show you what bridge dice.
[09:22] So it kind of show you what is possible when we put the different
[09:26] is possible when we put the different technology together to create even
[09:28] technology together to create even bigger bigger modules.
[09:30] So we can go up to 10x retical size in one days.
[09:35] to 10x retical size in one days.
[09:35] So but regarding power we introduced a
[09:39] So but regarding power we introduced a concept of power sit last year.
[09:41] concept of power sit last year.
[09:41] Basically is putting first and second
[09:44] Basically is putting first and second stage voltage regulator directly
[09:47] stage voltage regulator directly underneath the module itself to reduce
[09:50] underneath the module itself to reduce the power travel path to allow us to
[09:53] the power travel path to allow us to increase the overall power efficiency
[09:55] increase the overall power efficiency and deliver the power where is needed
[09:57] and deliver the power where is needed the most.
[10:01] So just doing electron may not be
[10:04] So just doing electron may not be enough.
[10:04] So we talk about putting chiplet
[10:07] enough.
[10:07] So we talk about putting chiplet together, putting HVM together, but we
[10:10] together, putting HVM together, but we do need more help.
[10:14] do need more help.
[10:14] The previous speaker Dr. H that talk about silicon photonics
[10:18] Dr. H that talk about silicon photonics and AAC share the same vision that we.
[10:21] and AAC share the same vision that we will believe that with chipless solution.
[10:24] will believe that with chipless solution and CPO, you can produce the next.
[10:27] and CPO, you can produce the next generation data center with the highest.
[10:29] generation data center with the highest bandwidth, highest compute power.
[10:31] bandwidth, highest compute power possible.
[10:33] possible. And we are providing tools for us to do that.
[10:36] And we are providing tools for us to do that for customers such as many of you.
[10:41] that for customers such as many of you in this room.
[10:43] in this room. We're trying to create easier way to do edge coupling putting.
[10:47] easier way to do edge coupling putting laser dire integration and doing 3D IC.
[10:50] laser dire integration and doing 3D IC integration through fan out between EIC.
[10:53] integration through fan out between EIC and PIC. And this creates a photonic.
[10:56] and PIC. And this creates a photonic engine right next to the package or.
[10:58] engine right next to the package or right next to the CPU CPU or GPU.
[11:01] right next to the CPU CPU or GPU chiplets.
[11:05] So we kind of talk about briefly about.
[11:08] So we kind of talk about briefly about the challenges that we face and we kind.
[11:10] the challenges that we face and we kind of talk about now the solution to.
[11:13] of talk about now the solution to increase the compute power and meet the.
[11:16] increase the compute power and meet the two to 7x performance require and the.
[11:19] Two to 7x performance require and the memory two to 10x require and the larger memory two to 10x require and the larger area that we need to put more and more area that we need to put more and more HVM and chiplets.
[11:29] We are using the HVM and chiplets.
[11:29] We are using the chiplet integration a heterogeneous chiplet integration a heterogeneous integration by leveraging the focus integration by leveraging the focus solution that we talked about earlier solution that we talked about earlier whether it's chip last or chip first whether it's chip last or chip first putting bridge silicon bridge between putting bridge silicon bridge between the die to become focus bridge doing the die to become focus bridge doing silicon photonics to reduce the power silicon photonics to reduce the power and increase bandwidth and to do panels and increase bandwidth and to do panels as large as 600 by 600 millimeter panel as large as 600 by 600 millimeter panel to get the maximum utilization so we can to get the maximum utilization so we can get to that large uh module that we seek get to that large uh module that we seek to meet the compute power demand of the to meet the compute power demand of the future and as far as the ecosystem is future and as far as the ecosystem is concerned we are now putting power SIP concerned we are now putting power SIP with VRM RM IVR integration backside with VRM RM IVR integration backside power behind the silicon structure and power behind the silicon structure and CPO to reduce the overall power by CPO to reduce the overall power by converting electron to photons and converting electron to photons and thermal is also something that we are
[12:20] thermal is also something that we are actively working on to discover new.
[12:22] actively working on to discover new material in terms of tin materials and possibly even working with silicon.
[12:28] vendor or microch cooling.
[12:33] and this kind of give you example of what is actually done at AAC today.
[12:40] So in summary we know AI and data continue to grow.
[12:43] This is what fuels semiconductor growth and how we believe by 2030 semiconductor will be a1 trillion dollar industry.
[12:50] And this is what shapes our life today.
[12:52] And I think collectively what AAC would like to do is share as much tools and ability to the audience for that creative solution,
[13:02] that innovation breakthrough that propel us to the next generation of AI innovation.
[13:08] Thank you so much.